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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i2s___tx___log_item.html">XI2s_Tx_LogItem</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This structure is used to store log events.  <a href="struct_x_i2s___tx___log_item.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i2s___tx___log.html">XI2s_Tx_Log</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The I2s Transmitter Log buffer.  <a href="struct_x_i2s___tx___log.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gab2803f3bdda4dec91e86a6f95c3ad7be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab2803f3bdda4dec91e86a6f95c3ad7be">XI2s_Tx_GetMaxChannels</a>(InstancePtr)</td></tr>
<tr class="memdesc:gab2803f3bdda4dec91e86a6f95c3ad7be"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the maximum number of I2S channels available.  <a href="#gab2803f3bdda4dec91e86a6f95c3ad7be">More...</a><br/></td></tr>
<tr class="separator:gab2803f3bdda4dec91e86a6f95c3ad7be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d785135b55f2d7fc8b26defaa45798b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga5d785135b55f2d7fc8b26defaa45798b">XI2s_Tx_IsI2sMaster</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga5d785135b55f2d7fc8b26defaa45798b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the I2S operating mode.  <a href="#ga5d785135b55f2d7fc8b26defaa45798b">More...</a><br/></td></tr>
<tr class="separator:ga5d785135b55f2d7fc8b26defaa45798b"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:ga5aae612901765b9ea6bb107e5b66b619"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga5aae612901765b9ea6bb107e5b66b619">XI2s_Tx_ChannelId</a> { <br/>
&#160;&#160;<a class="el" href="group__i2stx.html#gga5aae612901765b9ea6bb107e5b66b619a68360ea065dc9915804147319571fc59">XI2S_TX_CHID0</a> = 0, 
<a class="el" href="group__i2stx.html#gga5aae612901765b9ea6bb107e5b66b619aed6153a58db47e421c6b9e4503139f5b">XI2S_TX_CHID1</a>, 
<a class="el" href="group__i2stx.html#gga5aae612901765b9ea6bb107e5b66b619aabd0ee55dfa4069baa47050377781227">XI2S_TX_CHID2</a>, 
<a class="el" href="group__i2stx.html#gga5aae612901765b9ea6bb107e5b66b619af2f3fde5b16d7a77d36e18bc3f57d739">XI2S_TX_CHID3</a>, 
<br/>
&#160;&#160;<a class="el" href="group__i2stx.html#gga5aae612901765b9ea6bb107e5b66b619a252275e8db08efabd78dbe0c652605f4">XI2S_TX_NUM_CHANNELS</a>
<br/>
 }</td></tr>
<tr class="memdesc:ga5aae612901765b9ea6bb107e5b66b619"><td class="mdescLeft">&#160;</td><td class="mdescRight">These constants specify different channel ID's.  <a href="group__i2stx.html#ga5aae612901765b9ea6bb107e5b66b619">More...</a><br/></td></tr>
<tr class="separator:ga5aae612901765b9ea6bb107e5b66b619"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gab33cb9b421dbb85cef8a75a0dbf8a1dd"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab33cb9b421dbb85cef8a75a0dbf8a1dd">XI2s_Tx_CfgInitialize</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, <a class="el" href="struct_x_i2stx___config.html">XI2stx_Config</a> *CfgPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:gab33cb9b421dbb85cef8a75a0dbf8a1dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes the I2S Transmitter.  <a href="#gab33cb9b421dbb85cef8a75a0dbf8a1dd">More...</a><br/></td></tr>
<tr class="separator:gab33cb9b421dbb85cef8a75a0dbf8a1dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4321c85028de0ddb48f966d80325b10"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac4321c85028de0ddb48f966d80325b10">XI2s_Tx_Enable</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, u8 Enable)</td></tr>
<tr class="memdesc:gac4321c85028de0ddb48f966d80325b10"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables/disables the I2s Transmitter.  <a href="#gac4321c85028de0ddb48f966d80325b10">More...</a><br/></td></tr>
<tr class="separator:gac4321c85028de0ddb48f966d80325b10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8d2df1eb8affcff7f6b1eacad5016b39"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga8d2df1eb8affcff7f6b1eacad5016b39">XI2s_Tx_IntrEnable</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, u32 Mask)</td></tr>
<tr class="memdesc:ga8d2df1eb8affcff7f6b1eacad5016b39"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the specified interrupt of the I2s Transmitter.  <a href="#ga8d2df1eb8affcff7f6b1eacad5016b39">More...</a><br/></td></tr>
<tr class="separator:ga8d2df1eb8affcff7f6b1eacad5016b39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8f9b6a032bcb91ac82b9552f1ba3194"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab8f9b6a032bcb91ac82b9552f1ba3194">XI2s_Tx_IntrDisable</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, u32 Mask)</td></tr>
<tr class="memdesc:gab8f9b6a032bcb91ac82b9552f1ba3194"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function disables the specified interrupt of the I2s Transmitter.  <a href="#gab8f9b6a032bcb91ac82b9552f1ba3194">More...</a><br/></td></tr>
<tr class="separator:gab8f9b6a032bcb91ac82b9552f1ba3194"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga265a3458a6fd3232bba3df9f9341e3cd"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga265a3458a6fd3232bba3df9f9341e3cd">XI2s_Tx_SetChMux</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, <a class="el" href="group__i2stx.html#ga5aae612901765b9ea6bb107e5b66b619">XI2s_Tx_ChannelId</a> ChID, <a class="el" href="xi2stx_8h.html#a986ff4cc8196e017c2a11b5784cfa410">XI2s_Tx_ChMuxInput</a> InputSource)</td></tr>
<tr class="memdesc:ga265a3458a6fd3232bba3df9f9341e3cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the input source for the specified I2s channel.  <a href="#ga265a3458a6fd3232bba3df9f9341e3cd">More...</a><br/></td></tr>
<tr class="separator:ga265a3458a6fd3232bba3df9f9341e3cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacdd2c6678f1038ca76099cbcaebe1fde"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gacdd2c6678f1038ca76099cbcaebe1fde">XI2s_Tx_SetSclkOutDiv</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, u32 MClk, u32 Fs)</td></tr>
<tr class="memdesc:gacdd2c6678f1038ca76099cbcaebe1fde"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the SCLK Output divider value of the I2S timing generator.  <a href="#gacdd2c6678f1038ca76099cbcaebe1fde">More...</a><br/></td></tr>
<tr class="separator:gacdd2c6678f1038ca76099cbcaebe1fde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab68c1f16ccac1a678e93bd9c3bcdaed0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab68c1f16ccac1a678e93bd9c3bcdaed0">XI2s_Tx_GetAesChStatus</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, u8 *AesChStatusBuf)</td></tr>
<tr class="memdesc:gab68c1f16ccac1a678e93bd9c3bcdaed0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the captured AES Channel Status bits.  <a href="#gab68c1f16ccac1a678e93bd9c3bcdaed0">More...</a><br/></td></tr>
<tr class="separator:gab68c1f16ccac1a678e93bd9c3bcdaed0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1ee6ead0b1745ef400ec3e5198068aa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gae1ee6ead0b1745ef400ec3e5198068aa">XI2s_Tx_ClrAesChStatRegs</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:gae1ee6ead0b1745ef400ec3e5198068aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the captured AES Channel Status bits.  <a href="#gae1ee6ead0b1745ef400ec3e5198068aa">More...</a><br/></td></tr>
<tr class="separator:gae1ee6ead0b1745ef400ec3e5198068aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5c7f651728493e9ca5a13d824f47893"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gae5c7f651728493e9ca5a13d824f47893">XI2s_Tx_JustifyEnable</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, u8 Enable)</td></tr>
<tr class="memdesc:gae5c7f651728493e9ca5a13d824f47893"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables/disables the justification.  <a href="#gae5c7f651728493e9ca5a13d824f47893">More...</a><br/></td></tr>
<tr class="separator:gae5c7f651728493e9ca5a13d824f47893"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab101d38c979a17b2bd4540a3b418933d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab101d38c979a17b2bd4540a3b418933d">XI2s_Tx_Justify</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, <a class="el" href="xi2stx_8h.html#a2530845dc4c6c409a2cb7025beda590f">XI2s_Tx_Justification</a> Justify)</td></tr>
<tr class="memdesc:gab101d38c979a17b2bd4540a3b418933d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is to enable right/left justification.  <a href="#gab101d38c979a17b2bd4540a3b418933d">More...</a><br/></td></tr>
<tr class="separator:gab101d38c979a17b2bd4540a3b418933d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga408ca1dccbd6c8c87103ec3d2e97c5bc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat</a> (u8 I2stx_SrcBuf[])</td></tr>
<tr class="memdesc:ga408ca1dccbd6c8c87103ec3d2e97c5bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the array I2stx_SrcBuf which has the values of all the I2S Transmitter AES status registers, extracts the required bits and prints them.  <a href="#ga408ca1dccbd6c8c87103ec3d2e97c5bc">More...</a><br/></td></tr>
<tr class="separator:ga408ca1dccbd6c8c87103ec3d2e97c5bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a5815edce7bde17b937480d41849d02"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga2a5815edce7bde17b937480d41849d02">XI2s_Tx_LogWrite</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, <a class="el" href="group__i2stx.html#ga6aae04d874f9b352d54806ffba47b000">XI2s_Tx_LogEvt</a> Event, u8 Data)</td></tr>
<tr class="memdesc:ga2a5815edce7bde17b937480d41849d02"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes I2S Transmitter logs into the buffer.  <a href="#ga2a5815edce7bde17b937480d41849d02">More...</a><br/></td></tr>
<tr class="separator:ga2a5815edce7bde17b937480d41849d02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18ca2b281e98177be7e6062051cb352f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_i2s___tx___log_item.html">XI2s_Tx_LogItem</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga18ca2b281e98177be7e6062051cb352f">XI2s_Tx_LogRead</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga18ca2b281e98177be7e6062051cb352f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the next item in the logging buffer.  <a href="#ga18ca2b281e98177be7e6062051cb352f">More...</a><br/></td></tr>
<tr class="separator:ga18ca2b281e98177be7e6062051cb352f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa1a03db44d1813c7632b95ec83765d5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaaa1a03db44d1813c7632b95ec83765d5">XI2s_Tx_LogReset</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaaa1a03db44d1813c7632b95ec83765d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the contents of the logging buffer.  <a href="#gaaa1a03db44d1813c7632b95ec83765d5">More...</a><br/></td></tr>
<tr class="separator:gaaa1a03db44d1813c7632b95ec83765d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ecb01665e82e3373ad2de2085a8dc87"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga6ecb01665e82e3373ad2de2085a8dc87">XI2s_Tx_LogDisplay</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga6ecb01665e82e3373ad2de2085a8dc87"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints the contents of the logging buffer.  <a href="#ga6ecb01665e82e3373ad2de2085a8dc87">More...</a><br/></td></tr>
<tr class="separator:ga6ecb01665e82e3373ad2de2085a8dc87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad17911935c47159f6b1c144c3df63ce2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler</a> (void *InstancePtr)</td></tr>
<tr class="memdesc:gad17911935c47159f6b1c144c3df63ce2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the interrupt handler for the I2S Transmitter driver.  <a href="#gad17911935c47159f6b1c144c3df63ce2">More...</a><br/></td></tr>
<tr class="separator:gad17911935c47159f6b1c144c3df63ce2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ff9bb309a9e3902fbe95ce3bc48ac51"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga8ff9bb309a9e3902fbe95ce3bc48ac51">XI2s_Tx_SetHandler</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr, <a class="el" href="group__i2stx.html#ga826ab5acb6a522281f46f358fc908bf3">XI2s_Tx_HandlerType</a> HandlerType, <a class="el" href="xi2stx_8h.html#a9212fbef371b7c3d7eff45b842a3aaa9">XI2s_Tx_Callback</a> FuncPtr, void *CallbackRef)</td></tr>
<tr class="memdesc:ga8ff9bb309a9e3902fbe95ce3bc48ac51"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs an asynchronous callback function for the given HandlerType:  <a href="#ga8ff9bb309a9e3902fbe95ce3bc48ac51">More...</a><br/></td></tr>
<tr class="separator:ga8ff9bb309a9e3902fbe95ce3bc48ac51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4efbba75f40c33ec9a37a033c2592bd8"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga4efbba75f40c33ec9a37a033c2592bd8">XI2s_Tx_SelfTest</a> (<a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga4efbba75f40c33ec9a37a033c2592bd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a self-test on the driver/device.  <a href="#ga4efbba75f40c33ec9a37a033c2592bd8">More...</a><br/></td></tr>
<tr class="separator:ga4efbba75f40c33ec9a37a033c2592bd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0bbbcbd065d1e0348187ba03cb3b67fb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_i2stx___config.html">XI2stx_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga0bbbcbd065d1e0348187ba03cb3b67fb">XI2s_Tx_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:ga0bbbcbd065d1e0348187ba03cb3b67fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns a reference to an <a class="el" href="struct_x_i2stx___config.html" title="This typedef contains configuration information for the I2s Transmitter. ">XI2stx_Config</a> structure based on the core id, <em>DeviceId</em>.  <a href="#ga0bbbcbd065d1e0348187ba03cb3b67fb">More...</a><br/></td></tr>
<tr class="separator:ga0bbbcbd065d1e0348187ba03cb3b67fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
XI2S_Tx_Handlertype</h2></td></tr>
<tr class="memitem:ga826ab5acb6a522281f46f358fc908bf3"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga826ab5acb6a522281f46f358fc908bf3">XI2s_Tx_HandlerType</a> { <br/>
&#160;&#160;<a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3aee14491aed8a040a938a4a67e74bc6bd">XI2S_TX_HANDLER_AES_BLKCMPLT</a> = 0, 
<a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3a8172cb6e2a0d147df0f06a0eada66f8d">XI2S_TX_HANDLER_AES_BLKSYNCERR</a>, 
<a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3ab9374d0904c4cd4ac730b17fff220107">XI2S_TX_HANDLER_AES_CHSTSUPD</a>, 
<a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3a346f30997b8d6d69e215f08a6db8d4ac">XI2S_TX_HANDLER_AUD_UNDRFLW</a>, 
<br/>
&#160;&#160;<a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3a9dfc593232c7f0a4b318f14bd1680e6d">XI2S_TX_NUM_HANDLERS</a>
<br/>
 }</td></tr>
<tr class="memdesc:ga826ab5acb6a522281f46f358fc908bf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">these constants specify different types of handlers and is used to differentiate interrupt requests from the I2s Transmitter peripheral.  <a href="group__i2stx.html#ga826ab5acb6a522281f46f358fc908bf3">More...</a><br/></td></tr>
<tr class="separator:ga826ab5acb6a522281f46f358fc908bf3"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
AES Status and Register Masks and Shifts.For formats/line protocols</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp1b2fb0350ef57abc83c57475284f924a"></a>check the AES Standard specifications document. </p>
</td></tr>
<tr class="memitem:gacc72d75920ade372109d305286e1c5fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gacc72d75920ade372109d305286e1c5fb">XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gacc72d75920ade372109d305286e1c5fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use of Channel Status Block bit shift.  <a href="#gacc72d75920ade372109d305286e1c5fb">More...</a><br/></td></tr>
<tr class="separator:gacc72d75920ade372109d305286e1c5fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffd31964c7785f76f3c1e443e6f306dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaffd31964c7785f76f3c1e443e6f306dd">XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gacc72d75920ade372109d305286e1c5fb">XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT</a>)</td></tr>
<tr class="memdesc:gaffd31964c7785f76f3c1e443e6f306dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use of Channel Status Block mask.  <a href="#gaffd31964c7785f76f3c1e443e6f306dd">More...</a><br/></td></tr>
<tr class="separator:gaffd31964c7785f76f3c1e443e6f306dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed277941e701357e05662d27cf26f8e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaed277941e701357e05662d27cf26f8e4">XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:gaed277941e701357e05662d27cf26f8e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Linear PCM Identification bit shift.  <a href="#gaed277941e701357e05662d27cf26f8e4">More...</a><br/></td></tr>
<tr class="separator:gaed277941e701357e05662d27cf26f8e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61af06e74f87b278b69a501a972e68e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga61af06e74f87b278b69a501a972e68e8">XI2S_TX_AES_STS_LINEAR_PCM_ID_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaed277941e701357e05662d27cf26f8e4">XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT</a>)</td></tr>
<tr class="memdesc:ga61af06e74f87b278b69a501a972e68e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Linear PCM Identification mask.  <a href="#ga61af06e74f87b278b69a501a972e68e8">More...</a><br/></td></tr>
<tr class="separator:ga61af06e74f87b278b69a501a972e68e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78cc8bc6611969180c83c93f6a495896"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga78cc8bc6611969180c83c93f6a495896">XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:ga78cc8bc6611969180c83c93f6a495896"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio signal pre- emphasis bit shift.  <a href="#ga78cc8bc6611969180c83c93f6a495896">More...</a><br/></td></tr>
<tr class="separator:ga78cc8bc6611969180c83c93f6a495896"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36f5fabf2bf95db8602835cc95861fa5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga36f5fabf2bf95db8602835cc95861fa5">XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_MASK</a>&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT)</td></tr>
<tr class="memdesc:ga36f5fabf2bf95db8602835cc95861fa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio signal pre-emphasis mask.  <a href="#ga36f5fabf2bf95db8602835cc95861fa5">More...</a><br/></td></tr>
<tr class="separator:ga36f5fabf2bf95db8602835cc95861fa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa5b86b6aa7c49e9edc95ee095e99ae1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gafa5b86b6aa7c49e9edc95ee095e99ae1">XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT</a>&#160;&#160;&#160;(5)</td></tr>
<tr class="memdesc:gafa5b86b6aa7c49e9edc95ee095e99ae1"><td class="mdescLeft">&#160;</td><td class="mdescRight">lock indication bit shift  <a href="#gafa5b86b6aa7c49e9edc95ee095e99ae1">More...</a><br/></td></tr>
<tr class="separator:gafa5b86b6aa7c49e9edc95ee095e99ae1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ad2f825b0dda934666fd0c8e66de95f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga6ad2f825b0dda934666fd0c8e66de95f">XI2S_TX_AES_STS_LOCK_INDICATION_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gafa5b86b6aa7c49e9edc95ee095e99ae1">XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT</a>)</td></tr>
<tr class="memdesc:ga6ad2f825b0dda934666fd0c8e66de95f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lock indication mask.  <a href="#ga6ad2f825b0dda934666fd0c8e66de95f">More...</a><br/></td></tr>
<tr class="separator:ga6ad2f825b0dda934666fd0c8e66de95f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab03ab7ac0cf37ff3a8f57008ff6c8b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaab03ab7ac0cf37ff3a8f57008ff6c8b3">XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT</a>&#160;&#160;&#160;(6)</td></tr>
<tr class="memdesc:gaab03ab7ac0cf37ff3a8f57008ff6c8b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sampling Frequency 0 bit shift.  <a href="#gaab03ab7ac0cf37ff3a8f57008ff6c8b3">More...</a><br/></td></tr>
<tr class="separator:gaab03ab7ac0cf37ff3a8f57008ff6c8b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7938a13abaa67d6d136feabbd6014b1d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga7938a13abaa67d6d136feabbd6014b1d">XI2S_TX_AES_STS_SAMPLING_FREQ_E_MASK</a>&#160;&#160;&#160;(0x3 &lt;&lt; XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT)</td></tr>
<tr class="memdesc:ga7938a13abaa67d6d136feabbd6014b1d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sampling Frequency 0 mask.  <a href="#ga7938a13abaa67d6d136feabbd6014b1d">More...</a><br/></td></tr>
<tr class="separator:ga7938a13abaa67d6d136feabbd6014b1d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3e5272ba1cc19696a062a2261c7811d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga3e5272ba1cc19696a062a2261c7811d3">XI2S_TX_AES_STS_CH_MODE_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga3e5272ba1cc19696a062a2261c7811d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel mode bit shift.  <a href="#ga3e5272ba1cc19696a062a2261c7811d3">More...</a><br/></td></tr>
<tr class="separator:ga3e5272ba1cc19696a062a2261c7811d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa8d727003a8e7cc47d0a7e45f506518e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaa8d727003a8e7cc47d0a7e45f506518e">XI2S_TX_AES_STS_CH_MODE_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_AES_STS_CH_MODE_SHIFT)</td></tr>
<tr class="memdesc:gaa8d727003a8e7cc47d0a7e45f506518e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel mode mask.  <a href="#gaa8d727003a8e7cc47d0a7e45f506518e">More...</a><br/></td></tr>
<tr class="separator:gaa8d727003a8e7cc47d0a7e45f506518e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb8e06582adcf37c20a9db80d9d22881"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gabb8e06582adcf37c20a9db80d9d22881">XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT</a>&#160;&#160;&#160;(4)</td></tr>
<tr class="memdesc:gabb8e06582adcf37c20a9db80d9d22881"><td class="mdescLeft">&#160;</td><td class="mdescRight">User Bits Management bit shift.  <a href="#gabb8e06582adcf37c20a9db80d9d22881">More...</a><br/></td></tr>
<tr class="separator:gabb8e06582adcf37c20a9db80d9d22881"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4425bdbc5e0d0d757fb94635c60a6279"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga4425bdbc5e0d0d757fb94635c60a6279">XI2S_TX_AES_STS_USR_BITS_MGMT_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT)</td></tr>
<tr class="memdesc:ga4425bdbc5e0d0d757fb94635c60a6279"><td class="mdescLeft">&#160;</td><td class="mdescRight">User Bits Management mask.  <a href="#ga4425bdbc5e0d0d757fb94635c60a6279">More...</a><br/></td></tr>
<tr class="separator:ga4425bdbc5e0d0d757fb94635c60a6279"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a09ffa618e6590c9e82f91a49b4f68c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga7a09ffa618e6590c9e82f91a49b4f68c">XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga7a09ffa618e6590c9e82f91a49b4f68c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use of auxiliary sample bits bit shift.  <a href="#ga7a09ffa618e6590c9e82f91a49b4f68c">More...</a><br/></td></tr>
<tr class="separator:ga7a09ffa618e6590c9e82f91a49b4f68c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2792e6c77cf3427d9ba40ecafc84781c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga2792e6c77cf3427d9ba40ecafc84781c">XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_MASK</a>&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT)</td></tr>
<tr class="memdesc:ga2792e6c77cf3427d9ba40ecafc84781c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use of Auxiliary sample bits mask.  <a href="#ga2792e6c77cf3427d9ba40ecafc84781c">More...</a><br/></td></tr>
<tr class="separator:ga2792e6c77cf3427d9ba40ecafc84781c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16fae1ae006e75519d45a4dc31e2aca1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga16fae1ae006e75519d45a4dc31e2aca1">XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:ga16fae1ae006e75519d45a4dc31e2aca1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Source word length bit shift.  <a href="#ga16fae1ae006e75519d45a4dc31e2aca1">More...</a><br/></td></tr>
<tr class="separator:ga16fae1ae006e75519d45a4dc31e2aca1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeadd56e1eb2fe7f16e64d20f4cc658a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaeadd56e1eb2fe7f16e64d20f4cc658a2">XI2S_TX_AES_STS_SRC_WORD_LENGTH_MASK</a>&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT)</td></tr>
<tr class="memdesc:gaeadd56e1eb2fe7f16e64d20f4cc658a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Source word length mask.  <a href="#gaeadd56e1eb2fe7f16e64d20f4cc658a2">More...</a><br/></td></tr>
<tr class="separator:gaeadd56e1eb2fe7f16e64d20f4cc658a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d1071669dd6047ca5c4ed69c9dc78a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga2d1071669dd6047ca5c4ed69c9dc78a4">XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT</a>&#160;&#160;&#160;(6)</td></tr>
<tr class="memdesc:ga2d1071669dd6047ca5c4ed69c9dc78a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indication of Alignment level bit shift.  <a href="#ga2d1071669dd6047ca5c4ed69c9dc78a4">More...</a><br/></td></tr>
<tr class="separator:ga2d1071669dd6047ca5c4ed69c9dc78a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00224a5937919a23e18bac70be453341"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga00224a5937919a23e18bac70be453341">XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_MASK</a>&#160;&#160;&#160;(0x3 &lt;&lt; XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT)</td></tr>
<tr class="memdesc:ga00224a5937919a23e18bac70be453341"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indication of Alignment level mask.  <a href="#ga00224a5937919a23e18bac70be453341">More...</a><br/></td></tr>
<tr class="separator:ga00224a5937919a23e18bac70be453341"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ea48d72e9607d6d8d8056421054ee85"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga6ea48d72e9607d6d8d8056421054ee85">XI2S_TX_AES_STS_CH_NUM0_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga6ea48d72e9607d6d8d8056421054ee85"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel Number (0) bit shift.  <a href="#ga6ea48d72e9607d6d8d8056421054ee85">More...</a><br/></td></tr>
<tr class="separator:ga6ea48d72e9607d6d8d8056421054ee85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa34fe37e7fabe3dbe32d1cb3978a7ab3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaa34fe37e7fabe3dbe32d1cb3978a7ab3">XI2S_TX_AES_STS_CH_NUM0_MASK</a>&#160;&#160;&#160;(0x7F &lt;&lt; XI2S_TX_AES_STS_CH_NUM0_SHIFT)</td></tr>
<tr class="memdesc:gaa34fe37e7fabe3dbe32d1cb3978a7ab3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel Number (0) mask.  <a href="#gaa34fe37e7fabe3dbe32d1cb3978a7ab3">More...</a><br/></td></tr>
<tr class="separator:gaa34fe37e7fabe3dbe32d1cb3978a7ab3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa6c85a34557271fafd80989c4d16c3fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaa6c85a34557271fafd80989c4d16c3fa">XI2S_TX_AES_STS_MC_CH_MODE_SHIFT</a>&#160;&#160;&#160;(7)</td></tr>
<tr class="memdesc:gaa6c85a34557271fafd80989c4d16c3fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multichannel mode bit shift.  <a href="#gaa6c85a34557271fafd80989c4d16c3fa">More...</a><br/></td></tr>
<tr class="separator:gaa6c85a34557271fafd80989c4d16c3fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7444409e9557cb8d2fba5d04791cc90f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga7444409e9557cb8d2fba5d04791cc90f">XI2S_TX_AES_STS_MC_CH_MODE_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaa6c85a34557271fafd80989c4d16c3fa">XI2S_TX_AES_STS_MC_CH_MODE_SHIFT</a>)</td></tr>
<tr class="memdesc:ga7444409e9557cb8d2fba5d04791cc90f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multichannel mode mask.  <a href="#ga7444409e9557cb8d2fba5d04791cc90f">More...</a><br/></td></tr>
<tr class="separator:ga7444409e9557cb8d2fba5d04791cc90f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2119679a117b6557a57553bafb66fa8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga2119679a117b6557a57553bafb66fa8b">XI2S_TX_AES_STS_CH_NUM1_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga2119679a117b6557a57553bafb66fa8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel Number (1) bit shift.  <a href="#ga2119679a117b6557a57553bafb66fa8b">More...</a><br/></td></tr>
<tr class="separator:ga2119679a117b6557a57553bafb66fa8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b92225913f1d1397643d294b96a3e79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga0b92225913f1d1397643d294b96a3e79">XI2S_TX_AES_STS_CH_NUM1_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_AES_STS_CH_NUM1_SHIFT)</td></tr>
<tr class="memdesc:ga0b92225913f1d1397643d294b96a3e79"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel Number (1) mask.  <a href="#ga0b92225913f1d1397643d294b96a3e79">More...</a><br/></td></tr>
<tr class="separator:ga0b92225913f1d1397643d294b96a3e79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc365c9d82d007f429dbc2c3175ba469"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gabc365c9d82d007f429dbc2c3175ba469">XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT</a>&#160;&#160;&#160;(4)</td></tr>
<tr class="memdesc:gabc365c9d82d007f429dbc2c3175ba469"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multichannel mode number bit shift.  <a href="#gabc365c9d82d007f429dbc2c3175ba469">More...</a><br/></td></tr>
<tr class="separator:gabc365c9d82d007f429dbc2c3175ba469"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60bdf4661314ff81890dd36a51203c1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga60bdf4661314ff81890dd36a51203c1b">XI2S_TX_AES_STS_MC_CH_MODE_NUM_MASK</a>&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT)</td></tr>
<tr class="memdesc:ga60bdf4661314ff81890dd36a51203c1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multichannel mode number mask.  <a href="#ga60bdf4661314ff81890dd36a51203c1b">More...</a><br/></td></tr>
<tr class="separator:ga60bdf4661314ff81890dd36a51203c1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac59f23705e781eb6d2375f7793e05847"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac59f23705e781eb6d2375f7793e05847">XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gac59f23705e781eb6d2375f7793e05847"><td class="mdescLeft">&#160;</td><td class="mdescRight">Digital Reference Audio signal bit shift.  <a href="#gac59f23705e781eb6d2375f7793e05847">More...</a><br/></td></tr>
<tr class="separator:gac59f23705e781eb6d2375f7793e05847"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac284c05fb5e7d7ad0f7c571cceb92c44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac284c05fb5e7d7ad0f7c571cceb92c44">XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK</a>&#160;&#160;&#160;(0x3 &lt;&lt; XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT)</td></tr>
<tr class="memdesc:gac284c05fb5e7d7ad0f7c571cceb92c44"><td class="mdescLeft">&#160;</td><td class="mdescRight">Digital Reference Audio signal mask.  <a href="#gac284c05fb5e7d7ad0f7c571cceb92c44">More...</a><br/></td></tr>
<tr class="separator:gac284c05fb5e7d7ad0f7c571cceb92c44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga32a5c5c380f0add139e9973ca5509ea2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga32a5c5c380f0add139e9973ca5509ea2">XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:ga32a5c5c380f0add139e9973ca5509ea2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved but undefined (0) bit shift.  <a href="#ga32a5c5c380f0add139e9973ca5509ea2">More...</a><br/></td></tr>
<tr class="separator:ga32a5c5c380f0add139e9973ca5509ea2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab54c4d024eec7747b7fdf2a90082ab54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab54c4d024eec7747b7fdf2a90082ab54">XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga32a5c5c380f0add139e9973ca5509ea2">XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT</a>)</td></tr>
<tr class="memdesc:gab54c4d024eec7747b7fdf2a90082ab54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved but undefined (0) mask.  <a href="#gab54c4d024eec7747b7fdf2a90082ab54">More...</a><br/></td></tr>
<tr class="separator:gab54c4d024eec7747b7fdf2a90082ab54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1548ab3982c777016c42ae4a5666fd6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab1548ab3982c777016c42ae4a5666fd6">XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:gab1548ab3982c777016c42ae4a5666fd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sampling Frequency (1) bit shift.  <a href="#gab1548ab3982c777016c42ae4a5666fd6">More...</a><br/></td></tr>
<tr class="separator:gab1548ab3982c777016c42ae4a5666fd6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06846f7b8d66403d152212ba43f193d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga06846f7b8d66403d152212ba43f193d1">XI2S_TX_AES_STS_SAMPLING_FREQ_Q_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT)</td></tr>
<tr class="memdesc:ga06846f7b8d66403d152212ba43f193d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sampling Frequency (1) mask.  <a href="#ga06846f7b8d66403d152212ba43f193d1">More...</a><br/></td></tr>
<tr class="separator:ga06846f7b8d66403d152212ba43f193d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa41e86e16999bcb460a58866386e054"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gafa41e86e16999bcb460a58866386e054">XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT</a>&#160;&#160;&#160;(7)</td></tr>
<tr class="memdesc:gafa41e86e16999bcb460a58866386e054"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sampling Frequency scaling flag bit shift.  <a href="#gafa41e86e16999bcb460a58866386e054">More...</a><br/></td></tr>
<tr class="separator:gafa41e86e16999bcb460a58866386e054"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac50f0435d41fd0b486bb02013ece9bd1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac50f0435d41fd0b486bb02013ece9bd1">XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gafa41e86e16999bcb460a58866386e054">XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT</a>)</td></tr>
<tr class="memdesc:gac50f0435d41fd0b486bb02013ece9bd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sampling Frequency scaling flag mask.  <a href="#gac50f0435d41fd0b486bb02013ece9bd1">More...</a><br/></td></tr>
<tr class="separator:gac50f0435d41fd0b486bb02013ece9bd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60f5065e192f127698ebd215693532d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga60f5065e192f127698ebd215693532d2">XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga60f5065e192f127698ebd215693532d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved but undefined (1) bit shift.  <a href="#ga60f5065e192f127698ebd215693532d2">More...</a><br/></td></tr>
<tr class="separator:ga60f5065e192f127698ebd215693532d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2417522499255b6d277cf54940eb5873"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga2417522499255b6d277cf54940eb5873">XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_MASK</a>&#160;&#160;&#160;(0xFF &lt;&lt; XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT)</td></tr>
<tr class="memdesc:ga2417522499255b6d277cf54940eb5873"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved but undefined (1) mask.  <a href="#ga2417522499255b6d277cf54940eb5873">More...</a><br/></td></tr>
<tr class="separator:ga2417522499255b6d277cf54940eb5873"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd0c030f77a5fcb8c4a947a095bebff3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gadd0c030f77a5fcb8c4a947a095bebff3">XI2S_TX_AES_STS_ALPHANUM_CH_ORG_DATA_OFFSET</a>&#160;&#160;&#160;(6)</td></tr>
<tr class="memdesc:gadd0c030f77a5fcb8c4a947a095bebff3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Alphanumeric channel origin data register(s) offset.  <a href="#gadd0c030f77a5fcb8c4a947a095bebff3">More...</a><br/></td></tr>
<tr class="separator:gadd0c030f77a5fcb8c4a947a095bebff3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac420217f8cd0d4a9970399ae81cf01c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac420217f8cd0d4a9970399ae81cf01c1">XI2S_TX_AES_STS_ALPHANUM_CH_DEST_DATA_OFFSET</a>&#160;&#160;&#160;(10)</td></tr>
<tr class="memdesc:gac420217f8cd0d4a9970399ae81cf01c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Alphanumeric channel destination data bit shift.  <a href="#gac420217f8cd0d4a9970399ae81cf01c1">More...</a><br/></td></tr>
<tr class="separator:gac420217f8cd0d4a9970399ae81cf01c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77f91a5fe07d9b303b311f3c578b4f72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga77f91a5fe07d9b303b311f3c578b4f72">XI2S_TX_AES_STS_LOCAL_SAMPLE_ADDRCODE_OFFSET</a>&#160;&#160;&#160;(14)</td></tr>
<tr class="memdesc:ga77f91a5fe07d9b303b311f3c578b4f72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Local sample address code register(s) offset.  <a href="#ga77f91a5fe07d9b303b311f3c578b4f72">More...</a><br/></td></tr>
<tr class="separator:ga77f91a5fe07d9b303b311f3c578b4f72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga20282a1477a1bd5c341d125779741b53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga20282a1477a1bd5c341d125779741b53">XI2S_TX_AES_STS_TIMEOFDAY_SAMPLE_ADDRCODE_OFFSET</a>&#160;&#160;&#160;(18)</td></tr>
<tr class="memdesc:ga20282a1477a1bd5c341d125779741b53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time-of-day sample address code register(s) offset.  <a href="#ga20282a1477a1bd5c341d125779741b53">More...</a><br/></td></tr>
<tr class="separator:ga20282a1477a1bd5c341d125779741b53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1424825d020d189367c1d66634b3c704"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1424825d020d189367c1d66634b3c704">XI2S_TX_AES_STS_RELIABLE_FLAGS_OFFSET</a>&#160;&#160;&#160;(22)</td></tr>
<tr class="memdesc:ga1424825d020d189367c1d66634b3c704"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reliability flags bit shift.  <a href="#ga1424825d020d189367c1d66634b3c704">More...</a><br/></td></tr>
<tr class="separator:ga1424825d020d189367c1d66634b3c704"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5dd63d1443d92e1002b3a67cc6a1a84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gae5dd63d1443d92e1002b3a67cc6a1a84">XI2S_TX_AES_STS_CRC_CHAR_OFFSET</a>&#160;&#160;&#160;(23)</td></tr>
<tr class="memdesc:gae5dd63d1443d92e1002b3a67cc6a1a84"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cyclic redundancy check character bit shift.  <a href="#gae5dd63d1443d92e1002b3a67cc6a1a84">More...</a><br/></td></tr>
<tr class="separator:gae5dd63d1443d92e1002b3a67cc6a1a84"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafdbfe687b89e0cc67fd29d883d1778db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gafdbfe687b89e0cc67fd29d883d1778db">XI2S_TX_LOG_ITEM_BUFFER_SIZE</a>&#160;&#160;&#160;(256)</td></tr>
<tr class="memdesc:gafdbfe687b89e0cc67fd29d883d1778db"><td class="mdescLeft">&#160;</td><td class="mdescRight">@ name Log Item Buffer Size  <a href="#gafdbfe687b89e0cc67fd29d883d1778db">More...</a><br/></td></tr>
<tr class="separator:gafdbfe687b89e0cc67fd29d883d1778db"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
XI2s_Tx_LogEvt</h2></td></tr>
<tr class="memitem:ga6aae04d874f9b352d54806ffba47b000"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga6aae04d874f9b352d54806ffba47b000">XI2s_Tx_LogEvt</a> { <br/>
&#160;&#160;<a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a781f73933fba2f76caf5223ee7d7138a">XI2S_TX_AES_BLKCMPLT_EVT</a>, 
<a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000aa405c98ff185685b920bb0cb2b28a73c">XI2S_TX_AES_BLKSYNCERR_EVT</a>, 
<a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000abae6f4f36c3422aed7d6b6777f83d7cb">XI2S_TX_AES_CHSTSUPD_EVT</a>, 
<a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a0c8694f12ae4d34ddb805f6b4658a71d">XI2S_TX_AUD_UNDRFLW_EVT</a>, 
<br/>
&#160;&#160;<a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a0de22b2a681cf072923f5be2f0ab542d">XI2S_TX_LOG_EVT_INVALID</a>
<br/>
 }</td></tr>
<tr class="memdesc:ga6aae04d874f9b352d54806ffba47b000"><td class="mdescLeft">&#160;</td><td class="mdescRight">These constants specify different types of handlers and is used to differentiate interrupt requests from the I2S Transmitter peripheral.  <a href="group__i2stx.html#ga6aae04d874f9b352d54806ffba47b000">More...</a><br/></td></tr>
<tr class="separator:ga6aae04d874f9b352d54806ffba47b000"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Register Map</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp092729737d14686054aa21531a3582c6"></a>Register offsets for the XI2S_Transmitter device. </p>
</td></tr>
<tr class="memitem:ga71367f64a4d88ca4a118a76fdb9ad3c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga71367f64a4d88ca4a118a76fdb9ad3c2">XI2S_TX_CORE_VER_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:ga71367f64a4d88ca4a118a76fdb9ad3c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Version Register.  <a href="#ga71367f64a4d88ca4a118a76fdb9ad3c2">More...</a><br/></td></tr>
<tr class="separator:ga71367f64a4d88ca4a118a76fdb9ad3c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8b735fda830cc26a7c58d713191b588"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac8b735fda830cc26a7c58d713191b588">XI2S_TX_CORE_CFG_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:gac8b735fda830cc26a7c58d713191b588"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Configuration Register.  <a href="#gac8b735fda830cc26a7c58d713191b588">More...</a><br/></td></tr>
<tr class="separator:gac8b735fda830cc26a7c58d713191b588"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5433601a320e6d1725885e7311c0bab4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga5433601a320e6d1725885e7311c0bab4">XI2S_TX_CORE_CTRL_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga5433601a320e6d1725885e7311c0bab4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Control Register.  <a href="#ga5433601a320e6d1725885e7311c0bab4">More...</a><br/></td></tr>
<tr class="separator:ga5433601a320e6d1725885e7311c0bab4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae026183d4bfda7b544050c93cc14f431"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gae026183d4bfda7b544050c93cc14f431">XI2S_TX_IRQCTRL_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:gae026183d4bfda7b544050c93cc14f431"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Control Register.  <a href="#gae026183d4bfda7b544050c93cc14f431">More...</a><br/></td></tr>
<tr class="separator:gae026183d4bfda7b544050c93cc14f431"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0727cfd1d5dd6c4dc2957d380b82878"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaf0727cfd1d5dd6c4dc2957d380b82878">XI2S_TX_IRQSTS_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:gaf0727cfd1d5dd6c4dc2957d380b82878"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="#gaf0727cfd1d5dd6c4dc2957d380b82878">More...</a><br/></td></tr>
<tr class="separator:gaf0727cfd1d5dd6c4dc2957d380b82878"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a514342cc0cc00eb2d5de77f1c35831"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga0a514342cc0cc00eb2d5de77f1c35831">XI2S_TX_TMR_CTRL_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga0a514342cc0cc00eb2d5de77f1c35831"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S Timing Control Register.  <a href="#ga0a514342cc0cc00eb2d5de77f1c35831">More...</a><br/></td></tr>
<tr class="separator:ga0a514342cc0cc00eb2d5de77f1c35831"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab099dec92b378872d40f46d5d37bfce3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab099dec92b378872d40f46d5d37bfce3">XI2S_TX_CH01_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:gab099dec92b378872d40f46d5d37bfce3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 0/1 Control Register.  <a href="#gab099dec92b378872d40f46d5d37bfce3">More...</a><br/></td></tr>
<tr class="separator:gab099dec92b378872d40f46d5d37bfce3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14dd880ff140c74666a9cf9136379a09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga14dd880ff140c74666a9cf9136379a09">XI2S_TX_CH23_OFFSET</a>&#160;&#160;&#160;0x34</td></tr>
<tr class="memdesc:ga14dd880ff140c74666a9cf9136379a09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 2/3 Control Register.  <a href="#ga14dd880ff140c74666a9cf9136379a09">More...</a><br/></td></tr>
<tr class="separator:ga14dd880ff140c74666a9cf9136379a09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga670aa850785e57f081453ede1f4cb4e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga670aa850785e57f081453ede1f4cb4e8">XI2S_TX_CH45_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:ga670aa850785e57f081453ede1f4cb4e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 4/5 Control Register.  <a href="#ga670aa850785e57f081453ede1f4cb4e8">More...</a><br/></td></tr>
<tr class="separator:ga670aa850785e57f081453ede1f4cb4e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28be098b8367b7212b8a10d2738204df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga28be098b8367b7212b8a10d2738204df">XI2S_TX_CH67_OFFSET</a>&#160;&#160;&#160;0x3C</td></tr>
<tr class="memdesc:ga28be098b8367b7212b8a10d2738204df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 6/7 Control Register.  <a href="#ga28be098b8367b7212b8a10d2738204df">More...</a><br/></td></tr>
<tr class="separator:ga28be098b8367b7212b8a10d2738204df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c3299df5616dd53e12403b0c50332b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga4c3299df5616dd53e12403b0c50332b4">XI2S_TX_AES_CHSTS0_OFFSET</a>&#160;&#160;&#160;0x50</td></tr>
<tr class="memdesc:ga4c3299df5616dd53e12403b0c50332b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 0 Register.  <a href="#ga4c3299df5616dd53e12403b0c50332b4">More...</a><br/></td></tr>
<tr class="separator:ga4c3299df5616dd53e12403b0c50332b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b7803271c5d40b4131f36985ca44d7c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1b7803271c5d40b4131f36985ca44d7c">XI2S_TX_AES_CHSTS1_OFFSET</a>&#160;&#160;&#160;0x54</td></tr>
<tr class="memdesc:ga1b7803271c5d40b4131f36985ca44d7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 1 Register.  <a href="#ga1b7803271c5d40b4131f36985ca44d7c">More...</a><br/></td></tr>
<tr class="separator:ga1b7803271c5d40b4131f36985ca44d7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f71faf4e090ca874ebdd6faf8d45c58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga5f71faf4e090ca874ebdd6faf8d45c58">XI2S_TX_AES_CHSTS2_OFFSET</a>&#160;&#160;&#160;0x58</td></tr>
<tr class="memdesc:ga5f71faf4e090ca874ebdd6faf8d45c58"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 2 Register.  <a href="#ga5f71faf4e090ca874ebdd6faf8d45c58">More...</a><br/></td></tr>
<tr class="separator:ga5f71faf4e090ca874ebdd6faf8d45c58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac14aa59e8a02b5bbadd089909bfe8eef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac14aa59e8a02b5bbadd089909bfe8eef">XI2S_TX_AES_CHSTS3_OFFSET</a>&#160;&#160;&#160;0x5C</td></tr>
<tr class="memdesc:gac14aa59e8a02b5bbadd089909bfe8eef"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 3 Register.  <a href="#gac14aa59e8a02b5bbadd089909bfe8eef">More...</a><br/></td></tr>
<tr class="separator:gac14aa59e8a02b5bbadd089909bfe8eef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaecf7d1b7f8e2ea9002be176c2da7d11c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaecf7d1b7f8e2ea9002be176c2da7d11c">XI2S_TX_AES_CHSTS4_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:gaecf7d1b7f8e2ea9002be176c2da7d11c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 4 Register.  <a href="#gaecf7d1b7f8e2ea9002be176c2da7d11c">More...</a><br/></td></tr>
<tr class="separator:gaecf7d1b7f8e2ea9002be176c2da7d11c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ee4df6c437ca4892d784a41d3ac6933"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga5ee4df6c437ca4892d784a41d3ac6933">XI2S_TX_AES_CHSTS5_OFFSET</a>&#160;&#160;&#160;0x64</td></tr>
<tr class="memdesc:ga5ee4df6c437ca4892d784a41d3ac6933"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 5 Register.  <a href="#ga5ee4df6c437ca4892d784a41d3ac6933">More...</a><br/></td></tr>
<tr class="separator:ga5ee4df6c437ca4892d784a41d3ac6933"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Core Configuration Register masks and shifts</h2></td></tr>
<tr class="memitem:gadd00996211fa24b4ad1fe606ac9ca68b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gadd00996211fa24b4ad1fe606ac9ca68b">XI2S_TX_REG_CFG_MSTR_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gadd00996211fa24b4ad1fe606ac9ca68b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is I2S Master bit shift.  <a href="#gadd00996211fa24b4ad1fe606ac9ca68b">More...</a><br/></td></tr>
<tr class="separator:gadd00996211fa24b4ad1fe606ac9ca68b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3791b6a3ea448f12b7430b6717251216"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga3791b6a3ea448f12b7430b6717251216">XI2S_TX_REG_CFG_MSTR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gadd00996211fa24b4ad1fe606ac9ca68b">XI2S_TX_REG_CFG_MSTR_SHIFT</a>)</td></tr>
<tr class="memdesc:ga3791b6a3ea448f12b7430b6717251216"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is I2S Master mask.  <a href="#ga3791b6a3ea448f12b7430b6717251216">More...</a><br/></td></tr>
<tr class="separator:ga3791b6a3ea448f12b7430b6717251216"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad24a8b84c1cb1bc7b5b337c9983f06ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad24a8b84c1cb1bc7b5b337c9983f06ae">XI2S_TX_REG_CFG_NUM_CH_SHIFT</a>&#160;&#160;&#160;(8)</td></tr>
<tr class="memdesc:gad24a8b84c1cb1bc7b5b337c9983f06ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of channels bit shift.  <a href="#gad24a8b84c1cb1bc7b5b337c9983f06ae">More...</a><br/></td></tr>
<tr class="separator:gad24a8b84c1cb1bc7b5b337c9983f06ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15244aa7ed58929e6cfa985aa0925e0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga15244aa7ed58929e6cfa985aa0925e0b">XI2S_TX_REG_CFG_NUM_CH_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_REG_CFG_NUM_CH_SHIFT)</td></tr>
<tr class="memdesc:ga15244aa7ed58929e6cfa985aa0925e0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of channels mask.  <a href="#ga15244aa7ed58929e6cfa985aa0925e0b">More...</a><br/></td></tr>
<tr class="separator:ga15244aa7ed58929e6cfa985aa0925e0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadcbb270122beea24e73bd9e054037219"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gadcbb270122beea24e73bd9e054037219">XI2S_TX_REG_CFG_DWDTH_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:gadcbb270122beea24e73bd9e054037219"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S Data Width bit shift.  <a href="#gadcbb270122beea24e73bd9e054037219">More...</a><br/></td></tr>
<tr class="separator:gadcbb270122beea24e73bd9e054037219"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4aa6c0904241a95aedc1e304b461795"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad4aa6c0904241a95aedc1e304b461795">XI2S_TX_REG_CFG_DWDTH_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gadcbb270122beea24e73bd9e054037219">XI2S_TX_REG_CFG_DWDTH_SHIFT</a>)</td></tr>
<tr class="memdesc:gad4aa6c0904241a95aedc1e304b461795"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S Data Width mask.  <a href="#gad4aa6c0904241a95aedc1e304b461795">More...</a><br/></td></tr>
<tr class="separator:gad4aa6c0904241a95aedc1e304b461795"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Core Control Register masks and shifts</h2></td></tr>
<tr class="memitem:gab30f15e315f8427cbe5f70dcfc766d04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab30f15e315f8427cbe5f70dcfc766d04">XI2S_TX_REG_CTRL_EN_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gab30f15e315f8427cbe5f70dcfc766d04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module Enable bit shift.  <a href="#gab30f15e315f8427cbe5f70dcfc766d04">More...</a><br/></td></tr>
<tr class="separator:gab30f15e315f8427cbe5f70dcfc766d04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b2c881b163a551e9a2e691b2efbf298"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1b2c881b163a551e9a2e691b2efbf298">XI2S_TX_REG_CTRL_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gab30f15e315f8427cbe5f70dcfc766d04">XI2S_TX_REG_CTRL_EN_SHIFT</a>)</td></tr>
<tr class="memdesc:ga1b2c881b163a551e9a2e691b2efbf298"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module Enable mask.  <a href="#ga1b2c881b163a551e9a2e691b2efbf298">More...</a><br/></td></tr>
<tr class="separator:ga1b2c881b163a551e9a2e691b2efbf298"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8c9496196c2e60b679d772a5bb94bce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaf8c9496196c2e60b679d772a5bb94bce">XI2S_TX_REG_CTRL_JFE_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:gaf8c9496196c2e60b679d772a5bb94bce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Justification Enable or Disable shift.  <a href="#gaf8c9496196c2e60b679d772a5bb94bce">More...</a><br/></td></tr>
<tr class="separator:gaf8c9496196c2e60b679d772a5bb94bce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ea8f32a59f2631f40ae16a73ae81049"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1ea8f32a59f2631f40ae16a73ae81049">XI2S_TX_REG_CTRL_JFE_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaf8c9496196c2e60b679d772a5bb94bce">XI2S_TX_REG_CTRL_JFE_SHIFT</a>)</td></tr>
<tr class="memdesc:ga1ea8f32a59f2631f40ae16a73ae81049"><td class="mdescLeft">&#160;</td><td class="mdescRight">Justification Enable or Disable mask.  <a href="#ga1ea8f32a59f2631f40ae16a73ae81049">More...</a><br/></td></tr>
<tr class="separator:ga1ea8f32a59f2631f40ae16a73ae81049"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaedef85bd81cde3085348c033e9346d89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaedef85bd81cde3085348c033e9346d89">XI2S_TX_REG_CTRL_LORJF_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:gaedef85bd81cde3085348c033e9346d89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Left or Right Justification shift.  <a href="#gaedef85bd81cde3085348c033e9346d89">More...</a><br/></td></tr>
<tr class="separator:gaedef85bd81cde3085348c033e9346d89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga079cf019c32c23a6c9d4de4a1d3f79d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga079cf019c32c23a6c9d4de4a1d3f79d7">XI2S_TX_REG_CTRL_LORJF_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaedef85bd81cde3085348c033e9346d89">XI2S_TX_REG_CTRL_LORJF_SHIFT</a>)</td></tr>
<tr class="memdesc:ga079cf019c32c23a6c9d4de4a1d3f79d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Left or Right Justification mask.  <a href="#ga079cf019c32c23a6c9d4de4a1d3f79d7">More...</a><br/></td></tr>
<tr class="separator:ga079cf019c32c23a6c9d4de4a1d3f79d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Interrupt masks and shifts</h2></td></tr>
<tr class="memitem:ga474f94f8ce6c7957980f131727cb0b78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga474f94f8ce6c7957980f131727cb0b78">XI2S_TX_INTR_AES_BLKCMPLT_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga474f94f8ce6c7957980f131727cb0b78"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Complete Interrupt bit shift.  <a href="#ga474f94f8ce6c7957980f131727cb0b78">More...</a><br/></td></tr>
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<tr class="memitem:gad3a413e9c7d1c7be7eb5c970b2b1da8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad3a413e9c7d1c7be7eb5c970b2b1da8b">XI2S_TX_INTR_AES_BLKCMPLT_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga474f94f8ce6c7957980f131727cb0b78">XI2S_TX_INTR_AES_BLKCMPLT_SHIFT</a>)</td></tr>
<tr class="memdesc:gad3a413e9c7d1c7be7eb5c970b2b1da8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Complete Interrupt mask.  <a href="#gad3a413e9c7d1c7be7eb5c970b2b1da8b">More...</a><br/></td></tr>
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<tr class="memitem:ga2819f9d81091b1148adf69cae58bd75d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga2819f9d81091b1148adf69cae58bd75d">XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:ga2819f9d81091b1148adf69cae58bd75d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Synchronization Error Interrupt bit shift.  <a href="#ga2819f9d81091b1148adf69cae58bd75d">More...</a><br/></td></tr>
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<tr class="memitem:gad2a8cc76d84d195679304c51c9b39076"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad2a8cc76d84d195679304c51c9b39076">XI2S_TX_INTR_AES_BLKSYNCERR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga2819f9d81091b1148adf69cae58bd75d">XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT</a>)</td></tr>
<tr class="memdesc:gad2a8cc76d84d195679304c51c9b39076"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Synchronization Error Interrupt mask.  <a href="#gad2a8cc76d84d195679304c51c9b39076">More...</a><br/></td></tr>
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<tr class="memitem:ga4f0e12e2538d1ea42f12bd8e12fb8f83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga4f0e12e2538d1ea42f12bd8e12fb8f83">XI2S_TX_INTR_AES_CHSTSUPD_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:ga4f0e12e2538d1ea42f12bd8e12fb8f83"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status Updated Interrupt bit shift.  <a href="#ga4f0e12e2538d1ea42f12bd8e12fb8f83">More...</a><br/></td></tr>
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<tr class="memitem:ga957f3265c9bec698c9250d1e106795f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga957f3265c9bec698c9250d1e106795f9">XI2S_TX_INTR_AES_CHSTSUPD_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga4f0e12e2538d1ea42f12bd8e12fb8f83">XI2S_TX_INTR_AES_CHSTSUPD_SHIFT</a>)</td></tr>
<tr class="memdesc:ga957f3265c9bec698c9250d1e106795f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status Updated Interrupt mask.  <a href="#ga957f3265c9bec698c9250d1e106795f9">More...</a><br/></td></tr>
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<tr class="memitem:gacbe707ac375ce43702049440e0de4099"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gacbe707ac375ce43702049440e0de4099">XI2S_TX_INTR_AUDUNDRFLW_SHIFT</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:gacbe707ac375ce43702049440e0de4099"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Underflow Detected Interrupt bit shift.  <a href="#gacbe707ac375ce43702049440e0de4099">More...</a><br/></td></tr>
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<tr class="memitem:ga1389efbbe1bf1f0d834324564556f221"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1389efbbe1bf1f0d834324564556f221">XI2S_TX_INTR_AUDUNDRFLW_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gacbe707ac375ce43702049440e0de4099">XI2S_TX_INTR_AUDUNDRFLW_SHIFT</a>)</td></tr>
<tr class="memdesc:ga1389efbbe1bf1f0d834324564556f221"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Underflow Detected Interrupt mask.  <a href="#ga1389efbbe1bf1f0d834324564556f221">More...</a><br/></td></tr>
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<tr class="memitem:ga0de7bad6dd089f7401c230fbae6b78a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga0de7bad6dd089f7401c230fbae6b78a1">XI2S_TX_GINTR_EN_SHIFT</a>&#160;&#160;&#160;(31)</td></tr>
<tr class="memdesc:ga0de7bad6dd089f7401c230fbae6b78a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable bit shift.  <a href="#ga0de7bad6dd089f7401c230fbae6b78a1">More...</a><br/></td></tr>
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<tr class="memitem:gaafa069cfbe1276144cc6e24ead6166b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaafa069cfbe1276144cc6e24ead6166b4">XI2S_TX_GINTR_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga0de7bad6dd089f7401c230fbae6b78a1">XI2S_TX_GINTR_EN_SHIFT</a>)</td></tr>
<tr class="memdesc:gaafa069cfbe1276144cc6e24ead6166b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable mask.  <a href="#gaafa069cfbe1276144cc6e24ead6166b4">More...</a><br/></td></tr>
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I2S Timing Control Register masks and shifts</h2></td></tr>
<tr class="memitem:ga32c4ecf17c044ae8011084623588da27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga32c4ecf17c044ae8011084623588da27">XI2S_TX_REG_TMR_SCLKDIV_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga32c4ecf17c044ae8011084623588da27"><td class="mdescLeft">&#160;</td><td class="mdescRight">SClk Divider bit shift.  <a href="#ga32c4ecf17c044ae8011084623588da27">More...</a><br/></td></tr>
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<tr class="memitem:ga9ad611dd66000557282ecbe330b06290"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga9ad611dd66000557282ecbe330b06290">XI2S_TX_REG_TMR_SCLKDIV_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_REG_TMR_SCLKDIV_SHIFT)</td></tr>
<tr class="memdesc:ga9ad611dd66000557282ecbe330b06290"><td class="mdescLeft">&#160;</td><td class="mdescRight">SClk Divider mask.  <a href="#ga9ad611dd66000557282ecbe330b06290">More...</a><br/></td></tr>
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Audio Channel Control Register masks and shifts</h2></td></tr>
<tr class="memitem:ga6864d0fe8ae6f1b8841192c97694f032"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga6864d0fe8ae6f1b8841192c97694f032">XI2S_TX_REG_CHCTRL_CHMUX_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga6864d0fe8ae6f1b8841192c97694f032"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel MUX bit shift.  <a href="#ga6864d0fe8ae6f1b8841192c97694f032">More...</a><br/></td></tr>
<tr class="separator:ga6864d0fe8ae6f1b8841192c97694f032"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f8bc951ab906c7ff8c3242794df432d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga3f8bc951ab906c7ff8c3242794df432d">XI2S_TX_REG_CHCTRL_CHMUX_MASK</a>&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_REG_CHCTRL_CHMUX_SHIFT)</td></tr>
<tr class="memdesc:ga3f8bc951ab906c7ff8c3242794df432d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel MUX mask.  <a href="#ga3f8bc951ab906c7ff8c3242794df432d">More...</a><br/></td></tr>
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Register access macro definition</h2></td></tr>
<tr class="memitem:ga76cb896e1172bda01e10eb11f58e7753"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga76cb896e1172bda01e10eb11f58e7753">XI2s_Tx_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:ga76cb896e1172bda01e10eb11f58e7753"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#ga76cb896e1172bda01e10eb11f58e7753">More...</a><br/></td></tr>
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<tr class="memitem:ga0d0a46e656491896100303e61c472d01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga0d0a46e656491896100303e61c472d01">XI2s_Tx_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ga0d0a46e656491896100303e61c472d01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#ga0d0a46e656491896100303e61c472d01">More...</a><br/></td></tr>
<tr class="separator:ga0d0a46e656491896100303e61c472d01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga70bc2238ba573d955a77cf6752fa209a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="group__i2stx.html#ga76cb896e1172bda01e10eb11f58e7753">XI2s_Tx_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="memdesc:ga70bc2238ba573d955a77cf6752fa209a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a I2S Transmitter register.  <a href="#ga70bc2238ba573d955a77cf6752fa209a">More...</a><br/></td></tr>
<tr class="separator:ga70bc2238ba573d955a77cf6752fa209a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc89f508a120762f9abfd61105622c06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="group__i2stx.html#ga0d0a46e656491896100303e61c472d01">XI2s_Tx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:gabc89f508a120762f9abfd61105622c06"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a I2S Transmitter register.  <a href="#gabc89f508a120762f9abfd61105622c06">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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          <td class="memname">#define XI2S_TX_AES_CHSTS0_OFFSET&#160;&#160;&#160;0x50</td>
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<p>AES Channel Status 0 Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gae1ee6ead0b1745ef400ec3e5198068aa">XI2s_Tx_ClrAesChStatRegs()</a>, and <a class="el" href="group__i2stx.html#gab68c1f16ccac1a678e93bd9c3bcdaed0">XI2s_Tx_GetAesChStatus()</a>.</p>

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</div>
<a class="anchor" id="ga1b7803271c5d40b4131f36985ca44d7c"></a>
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          <td class="memname">#define XI2S_TX_AES_CHSTS1_OFFSET&#160;&#160;&#160;0x54</td>
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<p>AES Channel Status 1 Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gae1ee6ead0b1745ef400ec3e5198068aa">XI2s_Tx_ClrAesChStatRegs()</a>.</p>

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<a class="anchor" id="ga5f71faf4e090ca874ebdd6faf8d45c58"></a>
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          <td class="memname">#define XI2S_TX_AES_CHSTS2_OFFSET&#160;&#160;&#160;0x58</td>
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<p>AES Channel Status 2 Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gae1ee6ead0b1745ef400ec3e5198068aa">XI2s_Tx_ClrAesChStatRegs()</a>.</p>

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</div>
<a class="anchor" id="gac14aa59e8a02b5bbadd089909bfe8eef"></a>
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          <td class="memname">#define XI2S_TX_AES_CHSTS3_OFFSET&#160;&#160;&#160;0x5C</td>
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<p>AES Channel Status 3 Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gae1ee6ead0b1745ef400ec3e5198068aa">XI2s_Tx_ClrAesChStatRegs()</a>.</p>

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</div>
<a class="anchor" id="gaecf7d1b7f8e2ea9002be176c2da7d11c"></a>
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          <td class="memname">#define XI2S_TX_AES_CHSTS4_OFFSET&#160;&#160;&#160;0x60</td>
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<p>AES Channel Status 4 Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gae1ee6ead0b1745ef400ec3e5198068aa">XI2s_Tx_ClrAesChStatRegs()</a>.</p>

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</div>
<a class="anchor" id="ga5ee4df6c437ca4892d784a41d3ac6933"></a>
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          <td class="memname">#define XI2S_TX_AES_CHSTS5_OFFSET&#160;&#160;&#160;0x64</td>
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<p>AES Channel Status 5 Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gae1ee6ead0b1745ef400ec3e5198068aa">XI2s_Tx_ClrAesChStatRegs()</a>.</p>

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<a class="anchor" id="gac420217f8cd0d4a9970399ae81cf01c1"></a>
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          <td class="memname">#define XI2S_TX_AES_STS_ALPHANUM_CH_DEST_DATA_OFFSET&#160;&#160;&#160;(10)</td>
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<p>Alphanumeric channel destination data bit shift. </p>

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<a class="anchor" id="gadd0c030f77a5fcb8c4a947a095bebff3"></a>
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          <td class="memname">#define XI2S_TX_AES_STS_ALPHANUM_CH_ORG_DATA_OFFSET&#160;&#160;&#160;(6)</td>
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<p>Alphanumeric channel origin data register(s) offset. </p>

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          <td class="memname">#define XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_MASK&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT)</td>
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<p>Audio signal pre-emphasis mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

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<a class="anchor" id="ga78cc8bc6611969180c83c93f6a495896"></a>
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          <td class="memname">#define XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT&#160;&#160;&#160;(2)</td>
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<p>Audio signal pre- emphasis bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

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<a class="anchor" id="gaa8d727003a8e7cc47d0a7e45f506518e"></a>
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          <td class="memname">#define XI2S_TX_AES_STS_CH_MODE_MASK&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_AES_STS_CH_MODE_SHIFT)</td>
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<p>Channel mode mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

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<a class="anchor" id="ga3e5272ba1cc19696a062a2261c7811d3"></a>
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          <td class="memname">#define XI2S_TX_AES_STS_CH_MODE_SHIFT&#160;&#160;&#160;(0)</td>
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<p>Channel mode bit shift. </p>

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<a class="anchor" id="gaa34fe37e7fabe3dbe32d1cb3978a7ab3"></a>
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<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_CH_NUM0_MASK&#160;&#160;&#160;(0x7F &lt;&lt; XI2S_TX_AES_STS_CH_NUM0_SHIFT)</td>
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      </table>
</div><div class="memdoc">

<p>Channel Number (0) mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga6ea48d72e9607d6d8d8056421054ee85"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_CH_NUM0_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Channel Number (0) bit shift. </p>

</div>
</div>
<a class="anchor" id="ga0b92225913f1d1397643d294b96a3e79"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_CH_NUM1_MASK&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_AES_STS_CH_NUM1_SHIFT)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Channel Number (1) mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga2119679a117b6557a57553bafb66fa8b"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_CH_NUM1_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Channel Number (1) bit shift. </p>

</div>
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<a class="anchor" id="gae5dd63d1443d92e1002b3a67cc6a1a84"></a>
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<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_CRC_CHAR_OFFSET&#160;&#160;&#160;(23)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cyclic redundancy check character bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gac284c05fb5e7d7ad0f7c571cceb92c44"></a>
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<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK&#160;&#160;&#160;(0x3 &lt;&lt; XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT)</td>
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      </table>
</div><div class="memdoc">

<p>Digital Reference Audio signal mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gac59f23705e781eb6d2375f7793e05847"></a>
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<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Digital Reference Audio signal bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga00224a5937919a23e18bac70be453341"></a>
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<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_MASK&#160;&#160;&#160;(0x3 &lt;&lt; XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT)</td>
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      </table>
</div><div class="memdoc">

<p>Indication of Alignment level mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga2d1071669dd6047ca5c4ed69c9dc78a4"></a>
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          <td class="memname">#define XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT&#160;&#160;&#160;(6)</td>
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      </table>
</div><div class="memdoc">

<p>Indication of Alignment level bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga61af06e74f87b278b69a501a972e68e8"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_LINEAR_PCM_ID_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaed277941e701357e05662d27cf26f8e4">XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT</a>)</td>
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      </table>
</div><div class="memdoc">

<p>Linear PCM Identification mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gaed277941e701357e05662d27cf26f8e4"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT&#160;&#160;&#160;(1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Linear PCM Identification bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga77f91a5fe07d9b303b311f3c578b4f72"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_LOCAL_SAMPLE_ADDRCODE_OFFSET&#160;&#160;&#160;(14)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Local sample address code register(s) offset. </p>

</div>
</div>
<a class="anchor" id="ga6ad2f825b0dda934666fd0c8e66de95f"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_LOCK_INDICATION_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gafa5b86b6aa7c49e9edc95ee095e99ae1">XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT</a>)</td>
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      </table>
</div><div class="memdoc">

<p>Lock indication mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gafa5b86b6aa7c49e9edc95ee095e99ae1"></a>
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<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT&#160;&#160;&#160;(5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>lock indication bit shift </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga7444409e9557cb8d2fba5d04791cc90f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_MC_CH_MODE_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaa6c85a34557271fafd80989c4d16c3fa">XI2S_TX_AES_STS_MC_CH_MODE_SHIFT</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Multichannel mode mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga60bdf4661314ff81890dd36a51203c1b"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_MC_CH_MODE_NUM_MASK&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT)</td>
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      </table>
</div><div class="memdoc">

<p>Multichannel mode number mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gabc365c9d82d007f429dbc2c3175ba469"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT&#160;&#160;&#160;(4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Multichannel mode number bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gaa6c85a34557271fafd80989c4d16c3fa"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_MC_CH_MODE_SHIFT&#160;&#160;&#160;(7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Multichannel mode bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga1424825d020d189367c1d66634b3c704"></a>
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<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_RELIABLE_FLAGS_OFFSET&#160;&#160;&#160;(22)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reliability flags bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gab54c4d024eec7747b7fdf2a90082ab54"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga32a5c5c380f0add139e9973ca5509ea2">XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT</a>)</td>
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      </table>
</div><div class="memdoc">

<p>Reserved but undefined (0) mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga32a5c5c380f0add139e9973ca5509ea2"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT&#160;&#160;&#160;(2)</td>
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</div><div class="memdoc">

<p>Reserved but undefined (0) bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga2417522499255b6d277cf54940eb5873"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_MASK&#160;&#160;&#160;(0xFF &lt;&lt; XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT)</td>
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</div><div class="memdoc">

<p>Reserved but undefined (1) mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga60f5065e192f127698ebd215693532d2"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT&#160;&#160;&#160;(0)</td>
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      </table>
</div><div class="memdoc">

<p>Reserved but undefined (1) bit shift. </p>

</div>
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<a class="anchor" id="ga7938a13abaa67d6d136feabbd6014b1d"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_SAMPLING_FREQ_E_MASK&#160;&#160;&#160;(0x3 &lt;&lt; XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT)</td>
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      </table>
</div><div class="memdoc">

<p>Sampling Frequency 0 mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gaab03ab7ac0cf37ff3a8f57008ff6c8b3"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT&#160;&#160;&#160;(6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Sampling Frequency 0 bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga06846f7b8d66403d152212ba43f193d1"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_SAMPLING_FREQ_Q_MASK&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT)</td>
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</div><div class="memdoc">

<p>Sampling Frequency (1) mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gab1548ab3982c777016c42ae4a5666fd6"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT&#160;&#160;&#160;(3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Sampling Frequency (1) bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gac50f0435d41fd0b486bb02013ece9bd1"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gafa41e86e16999bcb460a58866386e054">XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT</a>)</td>
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      </table>
</div><div class="memdoc">

<p>Sampling Frequency scaling flag mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gafa41e86e16999bcb460a58866386e054"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT&#160;&#160;&#160;(7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Sampling Frequency scaling flag bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gaeadd56e1eb2fe7f16e64d20f4cc658a2"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_SRC_WORD_LENGTH_MASK&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Source word length mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga16fae1ae006e75519d45a4dc31e2aca1"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT&#160;&#160;&#160;(3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Source word length bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga20282a1477a1bd5c341d125779741b53"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_TIMEOFDAY_SAMPLE_ADDRCODE_OFFSET&#160;&#160;&#160;(18)</td>
        </tr>
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</div><div class="memdoc">

<p>Time-of-day sample address code register(s) offset. </p>

</div>
</div>
<a class="anchor" id="gaffd31964c7785f76f3c1e443e6f306dd"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gacc72d75920ade372109d305286e1c5fb">XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT</a>)</td>
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      </table>
</div><div class="memdoc">

<p>Use of Channel Status Block mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gacc72d75920ade372109d305286e1c5fb"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Use of Channel Status Block bit shift. </p>

</div>
</div>
<a class="anchor" id="ga2792e6c77cf3427d9ba40ecafc84781c"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_MASK&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT)</td>
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</div><div class="memdoc">

<p>Use of Auxiliary sample bits mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="ga7a09ffa618e6590c9e82f91a49b4f68c"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Use of auxiliary sample bits bit shift. </p>

</div>
</div>
<a class="anchor" id="ga4425bdbc5e0d0d757fb94635c60a6279"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2S_TX_AES_STS_USR_BITS_MGMT_MASK&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>User Bits Management mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gabb8e06582adcf37c20a9db80d9d22881"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT&#160;&#160;&#160;(4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>User Bits Management bit shift. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga408ca1dccbd6c8c87103ec3d2e97c5bc">XI2s_Tx_ReslveAesChStat()</a>.</p>

</div>
</div>
<a class="anchor" id="gab099dec92b378872d40f46d5d37bfce3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_CH01_OFFSET&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Audio Channel 0/1 Control Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga265a3458a6fd3232bba3df9f9341e3cd">XI2s_Tx_SetChMux()</a>.</p>

</div>
</div>
<a class="anchor" id="ga14dd880ff140c74666a9cf9136379a09"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_CH23_OFFSET&#160;&#160;&#160;0x34</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Audio Channel 2/3 Control Register. </p>

</div>
</div>
<a class="anchor" id="ga670aa850785e57f081453ede1f4cb4e8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_CH45_OFFSET&#160;&#160;&#160;0x38</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Audio Channel 4/5 Control Register. </p>

</div>
</div>
<a class="anchor" id="ga28be098b8367b7212b8a10d2738204df"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_CH67_OFFSET&#160;&#160;&#160;0x3C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Audio Channel 6/7 Control Register. </p>

</div>
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<a class="anchor" id="gac8b735fda830cc26a7c58d713191b588"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XI2S_TX_CORE_CFG_OFFSET&#160;&#160;&#160;0x04</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Core Configuration Register. </p>

</div>
</div>
<a class="anchor" id="ga5433601a320e6d1725885e7311c0bab4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_CORE_CTRL_OFFSET&#160;&#160;&#160;0x08</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Core Control Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gac4321c85028de0ddb48f966d80325b10">XI2s_Tx_Enable()</a>, <a class="el" href="group__i2stx.html#gab101d38c979a17b2bd4540a3b418933d">XI2s_Tx_Justify()</a>, and <a class="el" href="group__i2stx.html#gae5c7f651728493e9ca5a13d824f47893">XI2s_Tx_JustifyEnable()</a>.</p>

</div>
</div>
<a class="anchor" id="ga71367f64a4d88ca4a118a76fdb9ad3c2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_CORE_VER_OFFSET&#160;&#160;&#160;0x00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Core Version Register. </p>

</div>
</div>
<a class="anchor" id="gab2803f3bdda4dec91e86a6f95c3ad7be"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XI2s_Tx_GetMaxChannels</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, (<a class="code" href="group__i2stx.html#gac8b735fda830cc26a7c58d713191b588">XI2S_TX_CORE_CFG_OFFSET</a>))\</div>
<div class="line">          &amp; <a class="code" href="group__i2stx.html#ga15244aa7ed58929e6cfa985aa0925e0b">XI2S_TX_REG_CFG_NUM_CH_MASK</a>) &gt;&gt; <a class="code" href="group__i2stx.html#gad24a8b84c1cb1bc7b5b337c9983f06ae">XI2S_TX_REG_CFG_NUM_CH_SHIFT</a>)</div>
<div class="ttc" id="group__i2stx_html_gac8b735fda830cc26a7c58d713191b588"><div class="ttname"><a href="group__i2stx.html#gac8b735fda830cc26a7c58d713191b588">XI2S_TX_CORE_CFG_OFFSET</a></div><div class="ttdeci">#define XI2S_TX_CORE_CFG_OFFSET</div><div class="ttdoc">Core Configuration Register. </div><div class="ttdef"><b>Definition:</b> xi2stx_hw.h:46</div></div>
<div class="ttc" id="group__i2stx_html_gad24a8b84c1cb1bc7b5b337c9983f06ae"><div class="ttname"><a href="group__i2stx.html#gad24a8b84c1cb1bc7b5b337c9983f06ae">XI2S_TX_REG_CFG_NUM_CH_SHIFT</a></div><div class="ttdeci">#define XI2S_TX_REG_CFG_NUM_CH_SHIFT</div><div class="ttdoc">Maximum number of channels bit shift. </div><div class="ttdef"><b>Definition:</b> xi2stx_hw.h:75</div></div>
<div class="ttc" id="group__i2stx_html_ga70bc2238ba573d955a77cf6752fa209a"><div class="ttname"><a href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a></div><div class="ttdeci">#define XI2s_Tx_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a I2S Transmitter register. </div><div class="ttdef"><b>Definition:</b> xi2stx_hw.h:192</div></div>
<div class="ttc" id="group__i2stx_html_ga15244aa7ed58929e6cfa985aa0925e0b"><div class="ttname"><a href="group__i2stx.html#ga15244aa7ed58929e6cfa985aa0925e0b">XI2S_TX_REG_CFG_NUM_CH_MASK</a></div><div class="ttdeci">#define XI2S_TX_REG_CFG_NUM_CH_MASK</div><div class="ttdoc">Maximum number of channels mask. </div><div class="ttdef"><b>Definition:</b> xi2stx_hw.h:78</div></div>
</div><!-- fragment -->
<p>This macro reads the maximum number of I2S channels available. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Maximum number of I2S Channels.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__i2stx.html#gab2803f3bdda4dec91e86a6f95c3ad7be" title="This macro reads the maximum number of I2S channels available. ">XI2s_Tx_GetMaxChannels(XI2s_Tx *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__i2stx.html#ga4efbba75f40c33ec9a37a033c2592bd8">XI2s_Tx_SelfTest()</a>.</p>

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<a class="anchor" id="gaafa069cfbe1276144cc6e24ead6166b4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_GINTR_EN_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga0de7bad6dd089f7401c230fbae6b78a1">XI2S_TX_GINTR_EN_SHIFT</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Global Interrupt Enable mask. </p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga0de7bad6dd089f7401c230fbae6b78a1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_GINTR_EN_SHIFT&#160;&#160;&#160;(31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Global Interrupt Enable bit shift. </p>

</div>
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<a class="anchor" id="ga76cb896e1172bda01e10eb11f58e7753"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2s_Tx_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="gad3a413e9c7d1c7be7eb5c970b2b1da8b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_INTR_AES_BLKCMPLT_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga474f94f8ce6c7957980f131727cb0b78">XI2S_TX_INTR_AES_BLKCMPLT_SHIFT</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Block Complete Interrupt mask. </p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>, and <a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga474f94f8ce6c7957980f131727cb0b78"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_INTR_AES_BLKCMPLT_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Block Complete Interrupt bit shift. </p>

</div>
</div>
<a class="anchor" id="gad2a8cc76d84d195679304c51c9b39076"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_INTR_AES_BLKSYNCERR_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga2819f9d81091b1148adf69cae58bd75d">XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Block Synchronization Error Interrupt mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga2819f9d81091b1148adf69cae58bd75d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT&#160;&#160;&#160;(1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Block Synchronization Error Interrupt bit shift. </p>

</div>
</div>
<a class="anchor" id="ga957f3265c9bec698c9250d1e106795f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_INTR_AES_CHSTSUPD_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga4f0e12e2538d1ea42f12bd8e12fb8f83">XI2S_TX_INTR_AES_CHSTSUPD_SHIFT</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Channel Status Updated Interrupt mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga4f0e12e2538d1ea42f12bd8e12fb8f83"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_INTR_AES_CHSTSUPD_SHIFT&#160;&#160;&#160;(2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AES Channel Status Updated Interrupt bit shift. </p>

</div>
</div>
<a class="anchor" id="ga1389efbbe1bf1f0d834324564556f221"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_INTR_AUDUNDRFLW_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gacbe707ac375ce43702049440e0de4099">XI2S_TX_INTR_AUDUNDRFLW_SHIFT</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Audio Underflow Detected Interrupt mask. </p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>, and <a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="gacbe707ac375ce43702049440e0de4099"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_INTR_AUDUNDRFLW_SHIFT&#160;&#160;&#160;(3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Audio Underflow Detected Interrupt bit shift. </p>

</div>
</div>
<a class="anchor" id="gae026183d4bfda7b544050c93cc14f431"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_IRQCTRL_OFFSET&#160;&#160;&#160;0x10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Control Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gab8f9b6a032bcb91ac82b9552f1ba3194">XI2s_Tx_IntrDisable()</a>, <a class="el" href="group__i2stx.html#ga8d2df1eb8affcff7f6b1eacad5016b39">XI2s_Tx_IntrEnable()</a>, and <a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler()</a>.</p>

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</div>
<a class="anchor" id="gaf0727cfd1d5dd6c4dc2957d380b82878"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_IRQSTS_OFFSET&#160;&#160;&#160;0x14</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Status Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga5d785135b55f2d7fc8b26defaa45798b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2s_Tx_IsI2sMaster</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                          (<a class="code" href="group__i2stx.html#gac8b735fda830cc26a7c58d713191b588">XI2S_TX_CORE_CFG_OFFSET</a>)) \</div>
<div class="line">          &amp; <a class="code" href="group__i2stx.html#ga3791b6a3ea448f12b7430b6717251216">XI2S_TX_REG_CFG_MSTR_MASK</a>) ? TRUE : FALSE)</div>
<div class="ttc" id="group__i2stx_html_gac8b735fda830cc26a7c58d713191b588"><div class="ttname"><a href="group__i2stx.html#gac8b735fda830cc26a7c58d713191b588">XI2S_TX_CORE_CFG_OFFSET</a></div><div class="ttdeci">#define XI2S_TX_CORE_CFG_OFFSET</div><div class="ttdoc">Core Configuration Register. </div><div class="ttdef"><b>Definition:</b> xi2stx_hw.h:46</div></div>
<div class="ttc" id="group__i2stx_html_ga3791b6a3ea448f12b7430b6717251216"><div class="ttname"><a href="group__i2stx.html#ga3791b6a3ea448f12b7430b6717251216">XI2S_TX_REG_CFG_MSTR_MASK</a></div><div class="ttdeci">#define XI2S_TX_REG_CFG_MSTR_MASK</div><div class="ttdoc">Is I2S Master mask. </div><div class="ttdef"><b>Definition:</b> xi2stx_hw.h:72</div></div>
<div class="ttc" id="group__i2stx_html_ga70bc2238ba573d955a77cf6752fa209a"><div class="ttname"><a href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a></div><div class="ttdeci">#define XI2s_Tx_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a I2S Transmitter register. </div><div class="ttdef"><b>Definition:</b> xi2stx_hw.h:192</div></div>
</div><!-- fragment -->
<p>This macro returns the I2S operating mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE : is I2S Master</li>
<li>FALSE : is I2S Slave</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="group__i2stx.html#ga5d785135b55f2d7fc8b26defaa45798b" title="This macro returns the I2S operating mode. ">XI2s_Tx_IsI2sMaster(XI2s_Tx *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__i2stx.html#ga4efbba75f40c33ec9a37a033c2592bd8">XI2s_Tx_SelfTest()</a>.</p>

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<a class="anchor" id="gafdbfe687b89e0cc67fd29d883d1778db"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2S_TX_LOG_ITEM_BUFFER_SIZE&#160;&#160;&#160;(256)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>@ name Log Item Buffer Size </p>

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</div>
<a class="anchor" id="ga0d0a46e656491896100303e61c472d01"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2s_Tx_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="ga70bc2238ba573d955a77cf6752fa209a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI2s_Tx_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__i2stx.html#ga76cb896e1172bda01e10eb11f58e7753">XI2s_Tx_In32</a>((BaseAddress) + ((u32)RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a I2S Transmitter register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the I2S Transmitter core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 XI2S_Tx_ReadReg(u32 BaseAddress, u32 RegOffset) </dd></dl>

<p>Referenced by <a class="el" href="group__i2stx.html#gac4321c85028de0ddb48f966d80325b10">XI2s_Tx_Enable()</a>, <a class="el" href="group__i2stx.html#gab68c1f16ccac1a678e93bd9c3bcdaed0">XI2s_Tx_GetAesChStatus()</a>, <a class="el" href="group__i2stx.html#gab8f9b6a032bcb91ac82b9552f1ba3194">XI2s_Tx_IntrDisable()</a>, <a class="el" href="group__i2stx.html#ga8d2df1eb8affcff7f6b1eacad5016b39">XI2s_Tx_IntrEnable()</a>, <a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler()</a>, <a class="el" href="group__i2stx.html#gab101d38c979a17b2bd4540a3b418933d">XI2s_Tx_Justify()</a>, and <a class="el" href="group__i2stx.html#gae5c7f651728493e9ca5a13d824f47893">XI2s_Tx_JustifyEnable()</a>.</p>

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          <td class="memname">#define XI2S_TX_REG_CFG_DWDTH_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gadcbb270122beea24e73bd9e054037219">XI2S_TX_REG_CFG_DWDTH_SHIFT</a>)</td>
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<p>I2S Data Width mask. </p>

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          <td class="memname">#define XI2S_TX_REG_CFG_DWDTH_SHIFT&#160;&#160;&#160;(16)</td>
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<p>I2S Data Width bit shift. </p>

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          <td class="memname">#define XI2S_TX_REG_CFG_MSTR_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gadd00996211fa24b4ad1fe606ac9ca68b">XI2S_TX_REG_CFG_MSTR_SHIFT</a>)</td>
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<p>Is I2S Master mask. </p>

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          <td class="memname">#define XI2S_TX_REG_CFG_MSTR_SHIFT&#160;&#160;&#160;(0)</td>
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<p>Is I2S Master bit shift. </p>

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          <td class="memname">#define XI2S_TX_REG_CFG_NUM_CH_MASK&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_REG_CFG_NUM_CH_SHIFT)</td>
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<p>Maximum number of channels mask. </p>

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          <td class="memname">#define XI2S_TX_REG_CFG_NUM_CH_SHIFT&#160;&#160;&#160;(8)</td>
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<p>Maximum number of channels bit shift. </p>

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          <td class="memname">#define XI2S_TX_REG_CHCTRL_CHMUX_MASK&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_REG_CHCTRL_CHMUX_SHIFT)</td>
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      </table>
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<p>Channel MUX mask. </p>

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          <td class="memname">#define XI2S_TX_REG_CHCTRL_CHMUX_SHIFT&#160;&#160;&#160;(0)</td>
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<p>Channel MUX bit shift. </p>

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          <td class="memname">#define XI2S_TX_REG_CTRL_EN_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gab30f15e315f8427cbe5f70dcfc766d04">XI2S_TX_REG_CTRL_EN_SHIFT</a>)</td>
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      </table>
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<p>Module Enable mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gac4321c85028de0ddb48f966d80325b10">XI2s_Tx_Enable()</a>.</p>

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          <td class="memname">#define XI2S_TX_REG_CTRL_EN_SHIFT&#160;&#160;&#160;(0)</td>
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      </table>
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<p>Module Enable bit shift. </p>

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          <td class="memname">#define XI2S_TX_REG_CTRL_JFE_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaf8c9496196c2e60b679d772a5bb94bce">XI2S_TX_REG_CTRL_JFE_SHIFT</a>)</td>
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      </table>
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<p>Justification Enable or Disable mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gae5c7f651728493e9ca5a13d824f47893">XI2s_Tx_JustifyEnable()</a>.</p>

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          <td class="memname">#define XI2S_TX_REG_CTRL_JFE_SHIFT&#160;&#160;&#160;(1)</td>
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      </table>
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<p>Justification Enable or Disable shift. </p>

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          <td class="memname">#define XI2S_TX_REG_CTRL_LORJF_MASK&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaedef85bd81cde3085348c033e9346d89">XI2S_TX_REG_CTRL_LORJF_SHIFT</a>)</td>
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      </table>
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<p>Left or Right Justification mask. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gab101d38c979a17b2bd4540a3b418933d">XI2s_Tx_Justify()</a>.</p>

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          <td class="memname">#define XI2S_TX_REG_CTRL_LORJF_SHIFT&#160;&#160;&#160;(2)</td>
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<p>Left or Right Justification shift. </p>

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          <td class="memname">#define XI2S_TX_REG_TMR_SCLKDIV_MASK&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_REG_TMR_SCLKDIV_SHIFT)</td>
        </tr>
      </table>
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<p>SClk Divider mask. </p>

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          <td class="memname">#define XI2S_TX_REG_TMR_SCLKDIV_SHIFT&#160;&#160;&#160;(0)</td>
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<p>SClk Divider bit shift. </p>

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          <td class="memname">#define XI2S_TX_TMR_CTRL_OFFSET&#160;&#160;&#160;0x20</td>
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<p>I2S Timing Control Register. </p>

<p>Referenced by <a class="el" href="group__i2stx.html#gacdd2c6678f1038ca76099cbcaebe1fde">XI2s_Tx_SetSclkOutDiv()</a>.</p>

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          <td class="memname">#define XI2s_Tx_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="group__i2stx.html#ga0d0a46e656491896100303e61c472d01">XI2s_Tx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td>
        </tr>
      </table>
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<p>This macro writes a value to a I2S Transmitter register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the I2S Transmitter core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XI2S_Tx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) </dd></dl>

<p>Referenced by <a class="el" href="group__i2stx.html#gae1ee6ead0b1745ef400ec3e5198068aa">XI2s_Tx_ClrAesChStatRegs()</a>, <a class="el" href="group__i2stx.html#gac4321c85028de0ddb48f966d80325b10">XI2s_Tx_Enable()</a>, <a class="el" href="group__i2stx.html#gab8f9b6a032bcb91ac82b9552f1ba3194">XI2s_Tx_IntrDisable()</a>, <a class="el" href="group__i2stx.html#ga8d2df1eb8affcff7f6b1eacad5016b39">XI2s_Tx_IntrEnable()</a>, <a class="el" href="group__i2stx.html#gab101d38c979a17b2bd4540a3b418933d">XI2s_Tx_Justify()</a>, <a class="el" href="group__i2stx.html#gae5c7f651728493e9ca5a13d824f47893">XI2s_Tx_JustifyEnable()</a>, <a class="el" href="group__i2stx.html#ga265a3458a6fd3232bba3df9f9341e3cd">XI2s_Tx_SetChMux()</a>, and <a class="el" href="group__i2stx.html#gacdd2c6678f1038ca76099cbcaebe1fde">XI2s_Tx_SetSclkOutDiv()</a>.</p>

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<h2 class="groupheader">Enumeration Type Documentation</h2>
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          <td class="memname">enum <a class="el" href="group__i2stx.html#ga5aae612901765b9ea6bb107e5b66b619">XI2s_Tx_ChannelId</a></td>
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<p>These constants specify different channel ID's. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga5aae612901765b9ea6bb107e5b66b619a68360ea065dc9915804147319571fc59"></a>XI2S_TX_CHID0</em>&nbsp;</td><td class="fielddoc">
<p>Channel 0. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga5aae612901765b9ea6bb107e5b66b619aed6153a58db47e421c6b9e4503139f5b"></a>XI2S_TX_CHID1</em>&nbsp;</td><td class="fielddoc">
<p>Channel 1. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga5aae612901765b9ea6bb107e5b66b619aabd0ee55dfa4069baa47050377781227"></a>XI2S_TX_CHID2</em>&nbsp;</td><td class="fielddoc">
<p>Channel 2. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga5aae612901765b9ea6bb107e5b66b619af2f3fde5b16d7a77d36e18bc3f57d739"></a>XI2S_TX_CHID3</em>&nbsp;</td><td class="fielddoc">
<p>Channel 3. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga5aae612901765b9ea6bb107e5b66b619a252275e8db08efabd78dbe0c652605f4"></a>XI2S_TX_NUM_CHANNELS</em>&nbsp;</td><td class="fielddoc">
<p>Number of Channel ID's. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="group__i2stx.html#ga826ab5acb6a522281f46f358fc908bf3">XI2s_Tx_HandlerType</a></td>
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<p>these constants specify different types of handlers and is used to differentiate interrupt requests from the I2s Transmitter peripheral. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga826ab5acb6a522281f46f358fc908bf3aee14491aed8a040a938a4a67e74bc6bd"></a>XI2S_TX_HANDLER_AES_BLKCMPLT</em>&nbsp;</td><td class="fielddoc">
<p>AES Block Complete Handler. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga826ab5acb6a522281f46f358fc908bf3a8172cb6e2a0d147df0f06a0eada66f8d"></a>XI2S_TX_HANDLER_AES_BLKSYNCERR</em>&nbsp;</td><td class="fielddoc">
<p>AES Block Sync Error Handler. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga826ab5acb6a522281f46f358fc908bf3ab9374d0904c4cd4ac730b17fff220107"></a>XI2S_TX_HANDLER_AES_CHSTSUPD</em>&nbsp;</td><td class="fielddoc">
<p>AES Channel Status Updated Handler. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga826ab5acb6a522281f46f358fc908bf3a346f30997b8d6d69e215f08a6db8d4ac"></a>XI2S_TX_HANDLER_AUD_UNDRFLW</em>&nbsp;</td><td class="fielddoc">
<p>Audio Underflow Detected Handler. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga826ab5acb6a522281f46f358fc908bf3a9dfc593232c7f0a4b318f14bd1680e6d"></a>XI2S_TX_NUM_HANDLERS</em>&nbsp;</td><td class="fielddoc">
<p>Number of handler types. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="group__i2stx.html#ga6aae04d874f9b352d54806ffba47b000">XI2s_Tx_LogEvt</a></td>
        </tr>
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<p>These constants specify different types of handlers and is used to differentiate interrupt requests from the I2S Transmitter peripheral. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga6aae04d874f9b352d54806ffba47b000a781f73933fba2f76caf5223ee7d7138a"></a>XI2S_TX_AES_BLKCMPLT_EVT</em>&nbsp;</td><td class="fielddoc">
<p>AES Block Complete Event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga6aae04d874f9b352d54806ffba47b000aa405c98ff185685b920bb0cb2b28a73c"></a>XI2S_TX_AES_BLKSYNCERR_EVT</em>&nbsp;</td><td class="fielddoc">
<p>AES Block Sync Error Event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga6aae04d874f9b352d54806ffba47b000abae6f4f36c3422aed7d6b6777f83d7cb"></a>XI2S_TX_AES_CHSTSUPD_EVT</em>&nbsp;</td><td class="fielddoc">
<p>AES Channel Status Updated Event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga6aae04d874f9b352d54806ffba47b000a0c8694f12ae4d34ddb805f6b4658a71d"></a>XI2S_TX_AUD_UNDRFLW_EVT</em>&nbsp;</td><td class="fielddoc">
<p>Audio Underflow Detected Event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga6aae04d874f9b352d54806ffba47b000a0de22b2a681cf072923f5be2f0ab542d"></a>XI2S_TX_LOG_EVT_INVALID</em>&nbsp;</td><td class="fielddoc">
<p>Invalid Log Event. </p>
</td></tr>
</table>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">int XI2s_Tx_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_i2stx___config.html">XI2stx_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function initializes the I2S Transmitter. </p>
<p>This function must be called prior to using the core. Initialization of the I2S Transmitter includes setting up the instance data, and ensuring the hardware is in a quiescent state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the I2s Transmitter instance. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>points to the configuration structure associated with the I2s Transmitter. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS : if successful.</li>
<li>XST_FAILURE : otherwise.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="struct_x_i2s___tx.html#a27283d1e5773c1e61982e5501d93821d">XI2s_Tx::IsReady</a>, <a class="el" href="group__i2stx.html#gac4321c85028de0ddb48f966d80325b10">XI2s_Tx_Enable()</a>, and <a class="el" href="group__i2stx.html#ga4efbba75f40c33ec9a37a033c2592bd8">XI2s_Tx_SelfTest()</a>.</p>

<p>Referenced by <a class="el" href="xi2stx__selftest__example_8c.html#a3b48b73e19976c8d41c321471431f674">I2sSelfTestExample()</a>, and <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>.</p>

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          <td class="memname">void XI2s_Tx_ClrAesChStatRegs </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function clears the captured AES Channel Status bits. </p>
<p>This will clear all the 6 channel status registers.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__i2stx.html#ga4c3299df5616dd53e12403b0c50332b4">XI2S_TX_AES_CHSTS0_OFFSET</a>, <a class="el" href="group__i2stx.html#ga1b7803271c5d40b4131f36985ca44d7c">XI2S_TX_AES_CHSTS1_OFFSET</a>, <a class="el" href="group__i2stx.html#ga5f71faf4e090ca874ebdd6faf8d45c58">XI2S_TX_AES_CHSTS2_OFFSET</a>, <a class="el" href="group__i2stx.html#gac14aa59e8a02b5bbadd089909bfe8eef">XI2S_TX_AES_CHSTS3_OFFSET</a>, <a class="el" href="group__i2stx.html#gaecf7d1b7f8e2ea9002be176c2da7d11c">XI2S_TX_AES_CHSTS4_OFFSET</a>, <a class="el" href="group__i2stx.html#ga5ee4df6c437ca4892d784a41d3ac6933">XI2S_TX_AES_CHSTS5_OFFSET</a>, and <a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Tx_Enable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Enable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function enables/disables the I2s Transmitter. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the I2s Transmitter instance. </td></tr>
    <tr><td class="paramname">Enable</td><td>specifies TRUE/FALSE value to either enable or disable the I2s Transmitter.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="struct_x_i2s___tx.html#a904fc449f5c73cdb770020af91f97dce">XI2s_Tx::IsStarted</a>, <a class="el" href="group__i2stx.html#ga5433601a320e6d1725885e7311c0bab4">XI2S_TX_CORE_CTRL_OFFSET</a>, <a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>, <a class="el" href="group__i2stx.html#ga1b2c881b163a551e9a2e691b2efbf298">XI2S_TX_REG_CTRL_EN_MASK</a>, and <a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>, and <a class="el" href="group__i2stx.html#gab33cb9b421dbb85cef8a75a0dbf8a1dd">XI2s_Tx_CfgInitialize()</a>.</p>

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          <td class="memname">void XI2s_Tx_GetAesChStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>AesChStatusBuf</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function gets the captured AES Channel Status bits. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the I2s Transmitter instance. </td></tr>
    <tr><td class="paramname">AesChStatusBuf</td><td>is a pointer to a buffer that is used for writing the AES Channel Status bits, this needs to be allocated by user application</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="group__i2stx.html#ga4c3299df5616dd53e12403b0c50332b4">XI2S_TX_AES_CHSTS0_OFFSET</a>, and <a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>.</p>

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          <td class="memname">void XI2s_Tx_IntrDisable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function disables the specified interrupt of the I2s Transmitter. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the I2s Transmitter instance. </td></tr>
    <tr><td class="paramname">Mask</td><td>is a bit mask of the interrupts to be disabled.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section see"><dt>See Also</dt><dd>XI2stx_HW for the available interrupt masks. </dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="group__i2stx.html#gae026183d4bfda7b544050c93cc14f431">XI2S_TX_IRQCTRL_OFFSET</a>, <a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>, and <a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Tx_IntrEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function enables the specified interrupt of the I2s Transmitter. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the I2s Transmitter instance. </td></tr>
    <tr><td class="paramname">Mask</td><td>is a bit mask of the interrupts to be enabled.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section see"><dt>See Also</dt><dd>XI2stx_hw.h for the available interrupt masks. </dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="group__i2stx.html#gae026183d4bfda7b544050c93cc14f431">XI2S_TX_IRQCTRL_OFFSET</a>, <a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>, and <a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>.</p>

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          <td class="memname">void XI2s_Tx_IntrHandler </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function is the interrupt handler for the I2S Transmitter driver. </p>
<p>This handler reads the pending interrupt from the I2S Transmitter peripheral, determines the source of the interrupts, clears the interrupts and calls callbacks accordingly.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___tx.html#a1aca453ef57ad2e87ad957d59284e3c6">XI2s_Tx::AesBlkCmpltHandler</a>, <a class="el" href="struct_x_i2s___tx.html#a536a00ccba6a6ad94d9356917cece09b">XI2s_Tx::AesBlkSyncErrHandler</a>, <a class="el" href="struct_x_i2s___tx.html#a3c4d4247a9d7f33d9b213aca4620a763">XI2s_Tx::AudUndrflwHandler</a>, <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="struct_x_i2s___tx.html#a27283d1e5773c1e61982e5501d93821d">XI2s_Tx::IsReady</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a781f73933fba2f76caf5223ee7d7138a">XI2S_TX_AES_BLKCMPLT_EVT</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000aa405c98ff185685b920bb0cb2b28a73c">XI2S_TX_AES_BLKSYNCERR_EVT</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000abae6f4f36c3422aed7d6b6777f83d7cb">XI2S_TX_AES_CHSTSUPD_EVT</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a0c8694f12ae4d34ddb805f6b4658a71d">XI2S_TX_AUD_UNDRFLW_EVT</a>, <a class="el" href="group__i2stx.html#gad3a413e9c7d1c7be7eb5c970b2b1da8b">XI2S_TX_INTR_AES_BLKCMPLT_MASK</a>, <a class="el" href="group__i2stx.html#gad2a8cc76d84d195679304c51c9b39076">XI2S_TX_INTR_AES_BLKSYNCERR_MASK</a>, <a class="el" href="group__i2stx.html#ga957f3265c9bec698c9250d1e106795f9">XI2S_TX_INTR_AES_CHSTSUPD_MASK</a>, <a class="el" href="group__i2stx.html#ga1389efbbe1bf1f0d834324564556f221">XI2S_TX_INTR_AUDUNDRFLW_MASK</a>, <a class="el" href="group__i2stx.html#gae026183d4bfda7b544050c93cc14f431">XI2S_TX_IRQCTRL_OFFSET</a>, <a class="el" href="group__i2stx.html#gaf0727cfd1d5dd6c4dc2957d380b82878">XI2S_TX_IRQSTS_OFFSET</a>, <a class="el" href="group__i2stx.html#ga2a5815edce7bde17b937480d41849d02">XI2s_Tx_LogWrite()</a>, and <a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>.</p>

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          <td class="memname">void XI2s_Tx_Justify </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="xi2stx_8h.html#a2530845dc4c6c409a2cb7025beda590f">XI2s_Tx_Justification</a>&#160;</td>
          <td class="paramname"><em>Justify</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function is to enable right/left justification. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Transmitter instance. </td></tr>
    <tr><td class="paramname">Justify</td><td>is a enum to select the left or right justfication.<ul>
<li>XI2S_TX_JUSTIFY_LEFT : Left justication</li>
<li>XI2S_TX_JUSTIFY_RIGHT : Right justification</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="group__i2stx.html#ga5433601a320e6d1725885e7311c0bab4">XI2S_TX_CORE_CTRL_OFFSET</a>, <a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>, <a class="el" href="group__i2stx.html#ga079cf019c32c23a6c9d4de4a1d3f79d7">XI2S_TX_REG_CTRL_LORJF_MASK</a>, and <a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Tx_JustifyEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Enable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function enables/disables the justification. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XI2s Transmitter instance. </td></tr>
    <tr><td class="paramname">Enable</td><td>specifies TRUE/FALSE value to either enable or disable the justification.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="group__i2stx.html#ga5433601a320e6d1725885e7311c0bab4">XI2S_TX_CORE_CTRL_OFFSET</a>, <a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>, <a class="el" href="group__i2stx.html#ga1ea8f32a59f2631f40ae16a73ae81049">XI2S_TX_REG_CTRL_JFE_MASK</a>, and <a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>.</p>

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          <td class="memname">void XI2s_Tx_LogDisplay </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function prints the contents of the logging buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="struct_x_i2stx___config.html#a1cc38afcbc4c3273e97aca5b75d50641">XI2stx_Config::DeviceId</a>, <a class="el" href="struct_x_i2s___tx___log_item.html#a33c4f8732bfee9f467439c89af42043e">XI2s_Tx_LogItem::Event</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a781f73933fba2f76caf5223ee7d7138a">XI2S_TX_AES_BLKCMPLT_EVT</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000aa405c98ff185685b920bb0cb2b28a73c">XI2S_TX_AES_BLKSYNCERR_EVT</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000abae6f4f36c3422aed7d6b6777f83d7cb">XI2S_TX_AES_CHSTSUPD_EVT</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a0c8694f12ae4d34ddb805f6b4658a71d">XI2S_TX_AUD_UNDRFLW_EVT</a>, <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a0de22b2a681cf072923f5be2f0ab542d">XI2S_TX_LOG_EVT_INVALID</a>, and <a class="el" href="group__i2stx.html#ga18ca2b281e98177be7e6062051cb352f">XI2s_Tx_LogRead()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_i2s___tx___log_item.html">XI2s_Tx_LogItem</a>* XI2s_Tx_LogRead </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function returns the next item in the logging buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>When the buffer is filled, the next log item is returned. When the buffer is empty, NULL is returned.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___tx___log.html#a2211221b99c6181cc2c7452bf5d5a685">XI2s_Tx_Log::Head</a>, <a class="el" href="struct_x_i2s___tx___log.html#a1bd37896c4071876e22a70c6b695cba4">XI2s_Tx_Log::Items</a>, <a class="el" href="struct_x_i2s___tx.html#ad9ddb0184a08d6edd31d5ba71535b2be">XI2s_Tx::Log</a>, and <a class="el" href="struct_x_i2s___tx___log.html#a3b70e490297285e54c527723213cf66a">XI2s_Tx_Log::Tail</a>.</p>

<p>Referenced by <a class="el" href="group__i2stx.html#ga6ecb01665e82e3373ad2de2085a8dc87">XI2s_Tx_LogDisplay()</a>.</p>

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          <td class="memname">void XI2s_Tx_LogReset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function clears the contents of the logging buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___tx___log.html#a2211221b99c6181cc2c7452bf5d5a685">XI2s_Tx_Log::Head</a>, <a class="el" href="struct_x_i2s___tx___log.html#af465a471fb7d599165cb7265bb0c4f51">XI2s_Tx_Log::IsEnabled</a>, <a class="el" href="struct_x_i2s___tx.html#ad9ddb0184a08d6edd31d5ba71535b2be">XI2s_Tx::Log</a>, and <a class="el" href="struct_x_i2s___tx___log.html#a3b70e490297285e54c527723213cf66a">XI2s_Tx_Log::Tail</a>.</p>

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          <td class="memname">void XI2s_Tx_LogWrite </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2stx.html#ga6aae04d874f9b352d54806ffba47b000">XI2s_Tx_LogEvt</a>&#160;</td>
          <td class="paramname"><em>Event</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function writes I2S Transmitter logs into the buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> instance. </td></tr>
    <tr><td class="paramname">Event</td><td>is the log event type. </td></tr>
    <tr><td class="paramname">Data</td><td>is the log data.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Log write can be done only if the log is enabled. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___tx___log_item.html#a9c5069bf23673203a835dedfd62a319b">XI2s_Tx_LogItem::Data</a>, <a class="el" href="struct_x_i2s___tx___log_item.html#a33c4f8732bfee9f467439c89af42043e">XI2s_Tx_LogItem::Event</a>, <a class="el" href="struct_x_i2s___tx___log.html#a2211221b99c6181cc2c7452bf5d5a685">XI2s_Tx_Log::Head</a>, <a class="el" href="struct_x_i2s___tx___log.html#af465a471fb7d599165cb7265bb0c4f51">XI2s_Tx_Log::IsEnabled</a>, <a class="el" href="struct_x_i2s___tx___log.html#a1bd37896c4071876e22a70c6b695cba4">XI2s_Tx_Log::Items</a>, <a class="el" href="struct_x_i2s___tx.html#ad9ddb0184a08d6edd31d5ba71535b2be">XI2s_Tx::Log</a>, <a class="el" href="struct_x_i2s___tx___log.html#a3b70e490297285e54c527723213cf66a">XI2s_Tx_Log::Tail</a>, and <a class="el" href="group__i2stx.html#gga6aae04d874f9b352d54806ffba47b000a0de22b2a681cf072923f5be2f0ab542d">XI2S_TX_LOG_EVT_INVALID</a>.</p>

<p>Referenced by <a class="el" href="group__i2stx.html#gad17911935c47159f6b1c144c3df63ce2">XI2s_Tx_IntrHandler()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_i2stx___config.html">XI2stx_Config</a>* XI2s_Tx_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p>This function returns a reference to an <a class="el" href="struct_x_i2stx___config.html" title="This typedef contains configuration information for the I2s Transmitter. ">XI2stx_Config</a> structure based on the core id, <em>DeviceId</em>. </p>
<p>The return value will refer to an entry in the device configuration table defined in the xi2stx_g.c file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique core ID of the I2S Transmitter core for the lookup operation.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>returns a reference to a config record in the configuration table corresponding to <em>DeviceId</em>, or NULL if no match is found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xi2stx__selftest__example_8c.html#a3b48b73e19976c8d41c321471431f674">I2sSelfTestExample()</a>, and <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>.</p>

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          <td class="memname">void XI2s_Tx_ReslveAesChStat </td>
          <td>(</td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>I2stx_SrcBuf</em>[]</td><td>)</td>
          <td></td>
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<p>This function reads the array I2stx_SrcBuf which has the values of all the I2S Transmitter AES status registers, extracts the required bits and prints them. </p>
<p>Before calling this API, Call API XI2s_Tx_GetAesChStatus.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">I2stx_SrcBuf</td><td>is an array that contains the values of all the the AES Status registers. </td></tr>
  </table>
  </dd>
</dl>
<p>&lt; use of channel status block</p>
<p>&lt; linear PCM identification</p>
<p>&lt; audio signal Pre-emphasis</p>
<p>&lt; lock indication</p>
<p>&lt; sampling frequency</p>
<p>&lt; channel mode</p>
<p>&lt; user bits management</p>
<p>&lt; use of auxiliary sample bits</p>
<p>&lt; source word length</p>
<p>&lt; indication of alignment level</p>
<p>&lt; channel mode</p>
<p>&lt; Channel number 0</p>
<p>&lt; Channel number 1</p>
<p>&lt; multi channel1 mode number</p>
<p>&lt; digital audio reference signal</p>
<p>&lt; reserved but undefined</p>
<p>&lt; sampling frequency</p>
<p>&lt; sampling frequency scaling flag</p>
<p>&lt; reserved but undefined</p>
<p>&lt; Alphanumeric channel origin data</p>
<p>&lt; Alphanumeric channel destination data</p>
<p>&lt; Local sample address code</p>
<p>&lt; Time-of-day sample address code</p>
<p>&lt; Reliability flags</p>
<p>&lt; Cyclic redundancy check character </p>

<p>References <a class="el" href="group__i2stx.html#ga36f5fabf2bf95db8602835cc95861fa5">XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_MASK</a>, <a class="el" href="group__i2stx.html#ga78cc8bc6611969180c83c93f6a495896">XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT</a>, <a class="el" href="group__i2stx.html#gaa8d727003a8e7cc47d0a7e45f506518e">XI2S_TX_AES_STS_CH_MODE_MASK</a>, <a class="el" href="group__i2stx.html#gaa34fe37e7fabe3dbe32d1cb3978a7ab3">XI2S_TX_AES_STS_CH_NUM0_MASK</a>, <a class="el" href="group__i2stx.html#ga0b92225913f1d1397643d294b96a3e79">XI2S_TX_AES_STS_CH_NUM1_MASK</a>, <a class="el" href="group__i2stx.html#gae5dd63d1443d92e1002b3a67cc6a1a84">XI2S_TX_AES_STS_CRC_CHAR_OFFSET</a>, <a class="el" href="group__i2stx.html#gac284c05fb5e7d7ad0f7c571cceb92c44">XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK</a>, <a class="el" href="group__i2stx.html#gac59f23705e781eb6d2375f7793e05847">XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT</a>, <a class="el" href="group__i2stx.html#ga00224a5937919a23e18bac70be453341">XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_MASK</a>, <a class="el" href="group__i2stx.html#ga2d1071669dd6047ca5c4ed69c9dc78a4">XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT</a>, <a class="el" href="group__i2stx.html#ga61af06e74f87b278b69a501a972e68e8">XI2S_TX_AES_STS_LINEAR_PCM_ID_MASK</a>, <a class="el" href="group__i2stx.html#gaed277941e701357e05662d27cf26f8e4">XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT</a>, <a class="el" href="group__i2stx.html#ga6ad2f825b0dda934666fd0c8e66de95f">XI2S_TX_AES_STS_LOCK_INDICATION_MASK</a>, <a class="el" href="group__i2stx.html#gafa5b86b6aa7c49e9edc95ee095e99ae1">XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT</a>, <a class="el" href="group__i2stx.html#ga7444409e9557cb8d2fba5d04791cc90f">XI2S_TX_AES_STS_MC_CH_MODE_MASK</a>, <a class="el" href="group__i2stx.html#ga60bdf4661314ff81890dd36a51203c1b">XI2S_TX_AES_STS_MC_CH_MODE_NUM_MASK</a>, <a class="el" href="group__i2stx.html#gabc365c9d82d007f429dbc2c3175ba469">XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT</a>, <a class="el" href="group__i2stx.html#gaa6c85a34557271fafd80989c4d16c3fa">XI2S_TX_AES_STS_MC_CH_MODE_SHIFT</a>, <a class="el" href="group__i2stx.html#ga1424825d020d189367c1d66634b3c704">XI2S_TX_AES_STS_RELIABLE_FLAGS_OFFSET</a>, <a class="el" href="group__i2stx.html#gab54c4d024eec7747b7fdf2a90082ab54">XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_MASK</a>, <a class="el" href="group__i2stx.html#ga32a5c5c380f0add139e9973ca5509ea2">XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT</a>, <a class="el" href="group__i2stx.html#ga2417522499255b6d277cf54940eb5873">XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_MASK</a>, <a class="el" href="group__i2stx.html#ga7938a13abaa67d6d136feabbd6014b1d">XI2S_TX_AES_STS_SAMPLING_FREQ_E_MASK</a>, <a class="el" href="group__i2stx.html#gaab03ab7ac0cf37ff3a8f57008ff6c8b3">XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT</a>, <a class="el" href="group__i2stx.html#ga06846f7b8d66403d152212ba43f193d1">XI2S_TX_AES_STS_SAMPLING_FREQ_Q_MASK</a>, <a class="el" href="group__i2stx.html#gab1548ab3982c777016c42ae4a5666fd6">XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT</a>, <a class="el" href="group__i2stx.html#gac50f0435d41fd0b486bb02013ece9bd1">XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK</a>, <a class="el" href="group__i2stx.html#gafa41e86e16999bcb460a58866386e054">XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT</a>, <a class="el" href="group__i2stx.html#gaeadd56e1eb2fe7f16e64d20f4cc658a2">XI2S_TX_AES_STS_SRC_WORD_LENGTH_MASK</a>, <a class="el" href="group__i2stx.html#ga16fae1ae006e75519d45a4dc31e2aca1">XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT</a>, <a class="el" href="group__i2stx.html#gaffd31964c7785f76f3c1e443e6f306dd">XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_MASK</a>, <a class="el" href="group__i2stx.html#ga2792e6c77cf3427d9ba40ecafc84781c">XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_MASK</a>, <a class="el" href="group__i2stx.html#ga4425bdbc5e0d0d757fb94635c60a6279">XI2S_TX_AES_STS_USR_BITS_MGMT_MASK</a>, and <a class="el" href="group__i2stx.html#gabb8e06582adcf37c20a9db80d9d22881">XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT</a>.</p>

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          <td class="memname">int XI2s_Tx_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>Runs a self-test on the driver/device. </p>
<p>The self-test is reads the version register, configuration registers and verifies the values</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful i.e. if the self test passes.</li>
<li>XST_FAILURE if unsuccessful i.e. if the self test fails</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__i2stx.html#gab2803f3bdda4dec91e86a6f95c3ad7be">XI2s_Tx_GetMaxChannels</a>, and <a class="el" href="group__i2stx.html#ga5d785135b55f2d7fc8b26defaa45798b">XI2s_Tx_IsI2sMaster</a>.</p>

<p>Referenced by <a class="el" href="xi2stx__selftest__example_8c.html#a3b48b73e19976c8d41c321471431f674">I2sSelfTestExample()</a>, <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>, and <a class="el" href="group__i2stx.html#gab33cb9b421dbb85cef8a75a0dbf8a1dd">XI2s_Tx_CfgInitialize()</a>.</p>

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          <td class="memname">int XI2s_Tx_SetChMux </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2stx.html#ga5aae612901765b9ea6bb107e5b66b619">XI2s_Tx_ChannelId</a>&#160;</td>
          <td class="paramname"><em>ChID</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="xi2stx_8h.html#a986ff4cc8196e017c2a11b5784cfa410">XI2s_Tx_ChMuxInput</a>&#160;</td>
          <td class="paramname"><em>InputSource</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the input source for the specified I2s channel. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the I2s Transmitter instance. </td></tr>
    <tr><td class="paramname">ChID</td><td>specifies the I2s channel </td></tr>
    <tr><td class="paramname">InputSource</td><td>specifies the input source</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS : if successful.</li>
<li>XST_FAILURE : if the I2s channel is invalid. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="group__i2stx.html#gab099dec92b378872d40f46d5d37bfce3">XI2S_TX_CH01_OFFSET</a>, <a class="el" href="xi2stx_8h.html#a986ff4cc8196e017c2a11b5784cfa410a6f972c1a8f40e982c18bd08a568bb566">XI2S_TX_CHMUX_AXIS_01</a>, <a class="el" href="xi2stx_8h.html#a986ff4cc8196e017c2a11b5784cfa410a64201d5cdf20350b03a6e6e93da13173">XI2S_TX_CHMUX_AXIS_23</a>, <a class="el" href="xi2stx_8h.html#a986ff4cc8196e017c2a11b5784cfa410affaf08c53c7afa2b8d788dced78a32bc">XI2S_TX_CHMUX_AXIS_45</a>, <a class="el" href="xi2stx_8h.html#a986ff4cc8196e017c2a11b5784cfa410a84dfb423929256e872592e9c921fd099">XI2S_TX_CHMUX_AXIS_67</a>, <a class="el" href="xi2stx_8h.html#a986ff4cc8196e017c2a11b5784cfa410ae563eb5c2611dddc3b40f94aa619b991">XI2S_TX_CHMUX_WAVEGEN</a>, <a class="el" href="group__i2stx.html#gga5aae612901765b9ea6bb107e5b66b619a252275e8db08efabd78dbe0c652605f4">XI2S_TX_NUM_CHANNELS</a>, and <a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>.</p>

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          <td class="memname">int XI2s_Tx_SetHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__i2stx.html#ga826ab5acb6a522281f46f358fc908bf3">XI2s_Tx_HandlerType</a>&#160;</td>
          <td class="paramname"><em>HandlerType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="xi2stx_8h.html#a9212fbef371b7c3d7eff45b842a3aaa9">XI2s_Tx_Callback</a>&#160;</td>
          <td class="paramname"><em>FuncPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallbackRef</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>This function installs an asynchronous callback function for the given HandlerType: </p>
<pre>
HandlerType                              Callback Function
--------------------------------         -------------------------
(XI2S_TX_HANDLER_AES_BLKCMPLT)            AesBlkCmpltHandler
(XI2S_TX_HANDLER_AES_BLKSYNCERR)          AesBlkSyncErrHandler
(XI2S_TX_HANDLER_AES_CHSTSUPD)            AesChStsUpdHandler
(XI2S_TX_HANDLER_AUD_UNDRFLW)             AudUndrflwHandler
</pre><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i2s___tx.html" title="This typedef implements the I2s Transmitter driver instance data. ">XI2s_Tx</a> core instance. </td></tr>
    <tr><td class="paramname">HandlerType</td><td>specifies the type of handler. </td></tr>
    <tr><td class="paramname">FuncPtr</td><td>is a pointer to the callback function. </td></tr>
    <tr><td class="paramname">CallbackRef</td><td>is a reference pointer passed on actual calling of the callback function.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if callback function installed successfully.</li>
<li>XST_INVALID_PARAM when HandlerType is invalid.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Invoking this function for a handler that already has been installed replaces it with the new handler. </dd></dl>

<p>References <a class="el" href="struct_x_i2s___tx.html#a1aca453ef57ad2e87ad957d59284e3c6">XI2s_Tx::AesBlkCmpltHandler</a>, <a class="el" href="struct_x_i2s___tx.html#a536a00ccba6a6ad94d9356917cece09b">XI2s_Tx::AesBlkSyncErrHandler</a>, <a class="el" href="struct_x_i2s___tx.html#a3c4d4247a9d7f33d9b213aca4620a763">XI2s_Tx::AudUndrflwHandler</a>, <a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3aee14491aed8a040a938a4a67e74bc6bd">XI2S_TX_HANDLER_AES_BLKCMPLT</a>, <a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3a8172cb6e2a0d147df0f06a0eada66f8d">XI2S_TX_HANDLER_AES_BLKSYNCERR</a>, <a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3ab9374d0904c4cd4ac730b17fff220107">XI2S_TX_HANDLER_AES_CHSTSUPD</a>, <a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3a346f30997b8d6d69e215f08a6db8d4ac">XI2S_TX_HANDLER_AUD_UNDRFLW</a>, and <a class="el" href="group__i2stx.html#gga826ab5acb6a522281f46f358fc908bf3a9dfc593232c7f0a4b318f14bd1680e6d">XI2S_TX_NUM_HANDLERS</a>.</p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>.</p>

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          <td class="memname">u32 XI2s_Tx_SetSclkOutDiv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i2s___tx.html">XI2s_Tx</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>MClk</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Fs</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function calculates the SCLK Output divider value of the I2S timing generator. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the I2s Transmitter instance. </td></tr>
    <tr><td class="paramname">MClk</td><td>is the frequency of the MClk. </td></tr>
    <tr><td class="paramname">Fs</td><td>is the sampling frequency of the system. Divider value for the SCLK generation, MCLK/SCLK = SCLKOUT_DIV x 2 i.e. MCLK = 384xFs, SCLK = 48xFs (2x24bits) -&gt; SCLKOUT_DIV = MCLK/SCLK/2 = 4 Valid values are 1 through 15.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>- XST_FAILURE if SCLK Output divider is not calculated to be a positive integer.<ul>
<li>XST_SUCCESS, otherwise. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_i2stx___config.html#af68feefd4d9c6ccefa84679124e68735">XI2stx_Config::BaseAddress</a>, <a class="el" href="struct_x_i2s___tx.html#afe2bf6f0435f85ab88ec2912abe01137">XI2s_Tx::Config</a>, <a class="el" href="struct_x_i2stx___config.html#a3490395f577210a6eddf197e4466923a">XI2stx_Config::DWidth</a>, <a class="el" href="group__i2stx.html#ga0a514342cc0cc00eb2d5de77f1c35831">XI2S_TX_TMR_CTRL_OFFSET</a>, and <a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi2stx__intr__example_8c.html#a1d16f81e40091da2c2bf4b76f0a5adab">I2sTxIntrExample()</a>.</p>

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